Dual-mode transistor devices and methods for operating same

A device comprising:

• a plurality of transistor structures, transistor structures in the plurality including respectively:
• a semiconductor body including a channel region, a p-type source/drain terminal region adjacent a first side of the channel region and an n-type source/drain terminal region adjacent a second side of the channel region;
• a gate insulator on a surface of the semiconductor body over the channel region;
• a gate on the gate insulator over the channel region;
• and
• a first assist gate on the gate insulator disposed on a first side of the gate overlying a portion of the channel region adjacent the p-type source/drain terminal region, and a second assist gate on the gate insulator disposed on a second side of the gate overlying a portion of the channel region adjacent the n-type source/drain terminal region;
• and
• an assist gate driver coupled to the assist gates in the plurality of transistor structures which applies positive voltages to the first and second assist gates of some of the transistor structures to induce n-channel operation of the transistor structure, and negative voltages to the first and second assist gates of others of the transistor structures to induce p-channel operation of the transistor structure.

A method of manufacturing a dual-mode transistor device comprising:

• forming a semiconductor body including a channel region, a p-type source/drain terminal region adjacent a first side of the channel region and an n-type source/drain terminal region adjacent a second side of the channel region;
• forming a gate insulator on a surface of the semiconductor body over the channel region;
• forming a gate on the gate insulator over the channel region;
• and
• forming a first assist gate on the gate insulator disposed on a first side of the gate overlying a portion of the channel region adjacent the p-type source/drain terminal region, and a second assist gate on the gate insulator disposed on a second side of the gate overlying a portion of the channel region adjacent the n-type source/drain terminal region;
• and
• providing an assist gate driver electrically connected to the first and second assist gates to apply bias voltages to the first and second assist gates, configured to switch the transistor between an n-channel mode in which the bias voltages are positive and a p-channel mode in which the bias voltages are negative.