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US 9,287,402 B2Granted
Method of fabricating fin-field effect transistors (finFETs) having different fin widths
AssigneeSamsung Electronics Co., Ltd.
InventorsChang Woo Oh, Shincheol Min, Jongwook Lee, Choongho Lee
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Abstract
Provided are methods of forming field effect transistors. The method includes preparing a substrate with a first region and a second region, forming fin portions on the first and second regions, each of the fin portions protruding from the substrate and having a first width, forming a first mask pattern to expose the fin portions on the first region and cover the fin portions on the second region, and changing widths of the fin portions provided on the first region.
Claims31
A semiconductor device, comprising:
- a substrate including a first region and a second region;
- a first fin disposed on the first region and protruding from a top surface of the substrate;
- a second fin disposed on the second region and protruding from the top surface of the substrate;
- a first isolation contacting the first fin;
- and
- a second isolation contacting the second fin,
- wherein an upper portion of the first fin protrudes from the first isolation,
- an upper portion of the second fin protrudes from the second isolation,
- an N type transistor is in the first region,
- a P type transistor is in the second region, and
- a width of the upper portion of the first fin is different from a width of the upper portion of the second fin.
8 more elements
A semiconductor device comprising:
- a substrate including a first region and a second region;
- a first fin disposed on the first region and protruding from a top surface of the substrate;
- a second fin disposed on the first region and protruding from the top surface of the substrate;
- a third fin disposed on the second region and protruding from the top surface of the substrate;
- a fourth fin disposed on the second region and protruding from the top surface of the substrate;
- a gate electrode on the first fin, on the second fin, on the third fin and on the fourth fin, the gate electrode crossing the first fin, the second fin, the third fin and the fourth fin, the gate electrode including a first portion disposed between the first fin and the second fin and a second portion disposed between the third fin and the fourth fin;
- a first isolation disposed between the first fin and the second fin;
- and
- a second isolation disposed between the third fin and the fourth fin,
- wherein an upper portion of the first fin protrudes from the first isolation,
- an upper portion of the second fin protrudes from the first isolation,
- an upper portion of the third fin protrudes from the second isolation,
- an upper portion of the fourth fin protrudes from the second isolation,
- an N type transistor is in the first region,
- a P type transistor is in the second region, and
- a width of the first portion of the gate electrode is different from a width of the second portion of the gate electrode.
13 more elements
A semiconductor device, comprising:
- a substrate including a first region and a second region;
- a first fin disposed on the first region and protruding from a top surface of the substrate;
- a second fin disposed on the second region and protruding from the top surface of the substrate;
- a first isolation contacting the first fin;
- and
- a second isolation contacting the second fin,
- wherein an upper portion of the first fin protrudes from the first isolation and includes a first channel region,
- an upper portion of the second fin protrudes from the second isolation and includes a second channel region,
- an N type transistor is in the first region,
- a P type transistor is in the second region,
- a width of the upper portion of the first fin is different from a width of the upper portion of the second fin, and
- a height of the first fin is different from a height of the second fin.
9 more elements
A semiconductor device, comprising:
- a substrate including a first region and a second region;
- a first fin disposed on the first region and protruding from a top surface of the substrate, the first fin including a first upper portion and a first lower portion;
- a second fin disposed on the second region and protruding from the top surface of the substrate, the second fin including a second upper portion and a second lower portion;
- a first isolation contacting the first lower portion of the first fin;
- and
- a second isolation contacting the second lower portion of the second fin,
- wherein the first upper portion of the first fin protrudes from the first isolation,
- the second upper portion of the second fin protrudes from the second isolation,
- an N type transistor is in the first region,
- a P type transistor is in the second region,
- a width of the first lower portion of the first fin is greater than a width of the first upper portion of the first fin,
- a width of the second lower portion of the second fin is greater than a width of the second upper portion of the second fin,
- the width of the first upper portion of the first fin is different from the width of the second upper portion of the second fin, and
- a height of the first fin is different from a height of the second fin.
11 more elements
Dependencies are inferred from the claim text.