Transistor strain-inducing scheme
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTsz-Mei Kwok, Hsueh-Chang Sung, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee
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Abstract
A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.
Claims20
A transistor device, comprising:
- a gate structure disposed on a semiconductor substrate;
- a substantially v-shaped source/drain recess arranged in the semiconductor substrate alongside the gate structure, the source/drain recess having a bottom tip spaced beneath an upper surface of the semiconductor substrate and having outermost edges spaced beneath the upper surface of the semiconductor substrate on opposite sides of the bottom tip;
- a doped strain-inducing region disposed within the source/drain recess, wherein the doped strain-inducing region comprises a compound semiconductor material that is doped with n-type or p-type dopant impurities;
- and
- an un-doped strain-inducing region disposed within the source/drain recess under the doped strain-inducing region, wherein the un-doped strain-inducing region comprises the compound semiconductor material at a first stoichiometry near the bottom tip of the source/drain recess, and comprises the compound semiconductor material at a second, different stoichiometry near an outermost edge of the source/drain recess.
A transistor device, comprising:
- a gate structure disposed over a channel region of a semiconductor substrate, the channel region having a first doping type;
- a source/drain recess arranged in the semiconductor substrate alongside the gate structure;
- a doped silicon-germanium (SiGe) region disposed within the source/drain recess and having a second doping type which is opposite the first doping type;
- an un-doped SiGe region disposed within the source/drain recess and which underlies the doped SiGe region, wherein the un-doped SiGe region comprises different germanium concentrations at different locations within the source/drain recess;
- an outer un-doped SiGe layer abutting an upper surface of the source/drain recess and having a first germanium concentration;
- a lower un-doped SiGe layer abutting a bottom surface of the source/drain recess and having a second germanium concentration;
- and
- an inner un-doped SiGe layer between the outer un-doped SiGe layer and the lower un-doped SiGe layer and having a third germanium concentration, the third germanium concentration being higher than each of the first and second germanium concentrations.
A transistor device, comprising:
- a conductive gate structure disposed over a semiconductor substrate and separated from the semiconductor substrate by a gate dielectric;
- first and second source/drain recesses arranged in the semiconductor substrate on opposite sides of the conductive gate structure;
- a substantially v-shaped un-doped SiGe region lining lower and sidewall surfaces of the first or second source/drain recess, wherein a lower tip of the substantially v-shaped un-doped SiGe region is separated from upper outer tips of the substantially v-shaped un-doped SiGe region by an intermediate region having a stoichiometry that differs from the stoichiometries of the lower tip and upper outer tips;
- and
- a doped SiGe region disposed over the substantially v-shaped un-doped SiGe region and filling the first or second source/drain recess.
Dependencies are inferred from the claim text.