Semiconductor device and a bit line and the whole of a bit line contact plug having a vertically uniform profile
AssigneeSK hynix Inc.
InventorMun Mo Jeong
Life of this patent
Estimating the term…
Abstract
A semiconductor device comprises: a semiconductor substrate including a cell region and a peripheral region; an insulating film formed on the top portion of the semiconductor substrate of the cell region; a bit line contact hole including the etched insulating film to expose the semiconductor substrate; a bit line contact plug buried in the bit line contact plug; and a bit line formed on the top portion of the bit line contact plug to have the same width as that of the bit line contact plug. The thickness of the insulating film around a cell bit line is minimized so as to vertically form a profile of the cell bit line, thereby improving an overlay margin of a storage node contact and an active region.
Claims12
A semiconductor device comprising:
- a semiconductor substrate including a cell region and a peripheral region;
- a mask pattern disposed over the semiconductor substrate;
- a bit line contact hole extending through the mask pattern to expose the semiconductor substrate in the cell region;
- a bit line contact plug disposed within the bit line contact hole and directly contacting the semiconductor substrate;
- and
- a bit line disposed over the bit line contact plug,
- wherein the bit line and the entire bit line contact plug have the same width such that the bit line and the bit line contact plug have a vertically uniform profile, and
- wherein the width of the entire bit line contact plug is smaller than a width of the bit line contact hole.
A semiconductor device comprising:
- a substrate including a cell region and a peripheral region;
- a buried cell gate pattern disposed in the substrate in the cell region;
- a gate mask pattern disposed over the substrate in the cell region, the gate mask pattern defining the buried cell gate pattern;
- a bit line contact hole extending through the gate mask pattern to expose the substrate in the cell region;
- a bit line contact plug disposed within the bit line contact hole and directly contacting the substrate;
- an upper bit line pattern disposed over the bit line contact plug;
- and
- a storage node contact plug formed through the gate mask pattern and electrically coupled to the substrate,
- wherein a top level of the bit line contact plug is no higher than a top level of the gate mask pattern in the cell region,
- wherein the entire bit line contact plug and the upper bit line pattern have the same width, and
- wherein the width of the entire bit line contact plug is smaller than a width of the bit line contact hole.
Dependencies are inferred from the claim text.