Semiconductor device
AssigneeShindengen Electric Manufacturing Co., Ltd.
InventorNobuki Miyakoshi
Life of this patent
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Abstract
In a semiconductor device provided with a MOSFET part and a gate pad part, the gate pad part includes: a low resistance semiconductor layer; a drift layer; a poly-silicon layer constituting a conductor layer and a gate pad electrode formed above the drift layer over the whole area of the gate pad part with a field insulation layer interposed therebetween; and a gate oscillation suppressing structure, wherein the gate oscillation suppressing structure includes a p+-type diffusion region which is disposed along an outer peripheral portion of the gate pad part and is electrically connected with the a source electrode layer, and a p+-type diffusion region in a floating state and the p-type impurity non-diffusion regions which are alternately formed in the region surrounded by the p+-type diffusion region.
Claims18
A semiconductor device provided with an active element part and a gate pad part defined on a semiconductor substrate which is formed by laminating a low resistance semiconductor layer of a first conductive type or a second conductive type and a drift layer of the first conductive type to each other, wherein
- the active element part includes:
- the low resistance semiconductor layer;
- the drift layer formed on the low resistance semiconductor layer;
- a base region of the second conductive type formed on a surface of the drift layer;
- a high concentration impurity diffusion region of the first conductive type formed on a surface of the base region;
- a gate electrode layer formed on the base region sandwiched between the high concentration impurity diffusion region and the drift layer with a gate insulation layer interposed therebetween;
- and
- a first electrode layer formed in contact with a surface of the high concentration impurity diffusion region and the surface of the base region in a state where the first electrode layer is insulated from the gate electrode layer with an interlayer insulation layer interposed therebetween, and
- the gate pad part includes:
- the low resistance semiconductor layer;
- the drift layer formed on the low resistance semiconductor layer;
- a conductor layer formed above the drift layer over a whole area of the gate pad part with a field insulation layer interposed therebetween;
- and
- a gate oscillation suppressing structure formed on the surface of the drift layer, wherein
- the gate oscillation suppressing structure includes:
- a first impurity diffusion region of the second conductive type which is disposed along an outer peripheral portion of the gate pad part and is electrically connected with the first electrode layer, and a second impurity diffusion region of the second conductive type in a floating state and an impurity non-diffusion region of the second conductive type which are alternately formed in a region surrounded by the first impurity diffusion region of the second conductive type.
A semiconductor device provided with an active element part and a gate pad part defined on a semiconductor substrate which is formed by laminating a low resistance semiconductor layer of a first conductive type or a second conductive type and a drift layer of the first conductive type to each other, wherein
- the active element part includes:
- the low resistance semiconductor layer;
- the drift layer formed on the low resistance semiconductor layer;
- a base region of the second conductive type formed on a surface of the drift layer;
- a plurality of trenches formed such that the trenches open at the base region and reach the drift layer;
- a high concentration impurity diffusion region of the first conductive type arranged within the base region, exposing at least a portion thereof on inner peripheral surfaces of the trenches;
- a gate insulation layer formed on the inner peripheral surfaces of the trenches;
- a gate electrode layer embedded into the inside of the trenches with the gate insulation layer interposed therebetween;
- and
- a first electrode layer formed in contact with a surface of the high concentration impurity diffusion region and a surface of the base region in a state where the first electrode layer is insulated from the gate electrode layer with an interlayer insulation layer interposed therebetween, and
- the gate pad part includes:
- the low resistance semiconductor layer;
- the drift layer formed on the low resistance semiconductor layer;
- a conductor layer formed above the drift layer over a whole area of the gate pad part with a field insulation layer interposed therebetween;
- and
- a gate oscillation suppressing structure formed on the surface of the drift layer, wherein
- the gate oscillation suppressing structure includes:
- a first impurity diffusion region of the second conductive type which is disposed along an outer peripheral portion of the gate pad part and is electrically connected with the first electrode layer and a second impurity diffusion region of the second conductive type in a floating state and an impurity non-diffusion region of the second conductive type which are alternately formed in a region surrounded by the first impurity diffusion region of the second conductive type.
Dependencies are inferred from the claim text.