Multi-fin device and method of making same

A transistor comprising:

• a dielectric layer having a first portion, a second portion and a third portion;
• a first semiconductor fin in the dielectric layer, the first semiconductor fin having a first sidewall and further having a second sidewall adjacent to, and extending a first distance over, the first portion of the dielectric layer;
• a second semiconductor fin in the dielectric layer between the first portion and second portion of the dielectric layer, the second semiconductor fin extending the first distance above the first and second portions of the dielectric layer;
• a third semiconductor fin in the dielectric layer between the second portion and third portion of the dielectric layer, the third semiconductor fin having a first sidewall disposed at, and extending the first distance above, the second portion of the dielectric layer, and further having a top surface, and a second sidewall disposed at the third portion of the dielectric layer, the third portion of the dielectric layer having a top surface coplanar with the top surface of the third semiconductor fin;
• a gate structure extending contiguously over the first, second and third semiconductor fins, wherein the gate structure contacts the first semiconductor fin on a top surface and second sidewall of the first semiconductor fin, wherein the gate structure contacts the second semiconductor fin on a top surface and first and second sidewalls of the second semiconductor fin, and wherein the gate structure contacts the top surface and the first sidewall of the third semiconductor fin;
• a source region distributed in the first, second and third semiconductor fins;
• and
• a drain region distributed in the first, second and third semiconductor fins;
• wherein the gate structure is configured to control a single transistor comprising the first semiconductor fin, the second semiconductor fin, the third semiconductor fin, the source region and the drain region.

A device comprising:

• a substrate having a plurality of fins, each fin of the plurality of fins having a substantially equal height and each fin having a top surface, a sidewall, a source region and drain region, an upper portion of the sidewall being substantially orthogonal to a major surface of the substrate, and a lower portion of the sidewall being non-orthogonal to the major surface of the substrate;
• a first dielectric region disposed between a first fin of the plurality of fins and a second fin of the plurality of fins, the first dielectric region having a top surface substantially planar with the top surface of the first fin and the second fin;
• a second dielectric region disposed between the second fin and a third fin of the plurality of fins, the second dielectric region having a top surface below the top surface of the second fin and the third fin;
• a continuous gate structure overlying the plurality of fins, the continuous gate structure being adjacent to the top surface of each of the plurality of fins, the continuous gate structure further disposed on the top surface of the first dielectric region and the top surface of the second dielectric region;
• a first continuous metal layer overlying the source regions of the first, second and third fins and forming a single source region of a single finFET transistor that comprises the first, second and third fins;
• and
• a second continuous metal layer overlying the drain regions of the first, second and third fins and forming a drain source region of the single finFET transistor.