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US 9,287,380 B2Granted
Gate electrode having a capping layer
AssigneeIntel Corporation
InventorsGilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
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Abstract
A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.
Claims10
A semiconductor transistor, comprising:
- a substrate;
- a transition oxide layer disposed on the substrate;
- a high-k dielectric material layer disposed on the transition oxide layer, the high-k dielectric material layer having a thickness approximately in the range of 5-25 Angstroms;
- a barrier layer disposed on the high-k dielectric material layer;
- a capping layer disposed on the barrier layer and comprising a material different than the barrier layer, wherein the capping layer is formed of one material which includes germanium, silicon germanium, silicon nitride, and amorphous silicon;
- and
- a gate electrode disposed above the capping layer and comprising a material different than the capping layer, wherein the gate electrode comprises a workfunction controlling metal;
- wherein a thickness of the barrier layer is less than 25 Angstroms.
5 more elements
A semiconductor transistor, comprising:
- a semiconductor body formed on a substrate, the semiconductor body having a top surface and a pair of laterally opposite sidewalls;
- a transition oxide layer disposed on the top surface and the sidewalls of the semiconductor body;
- a high-k dielectric material layer disposed on the transition oxide layer, the high-k dielectric material layer having a thickness approximately in the range of 5-25 Angstroms;
- a barrier layer disposed on the high-k dielectric material layer;
- a capping layer disposed on the barrier layer and comprising a material different than the barrier layer, wherein the capping layer is formed of one material which includes germanium, silicon germanium, silicon nitride, and amorphous silicon;
- and
- a gate electrode disposed above the capping layer and comprising a material different than the capping layer, wherein the gate electrode comprises a workfunction controlling metal;
- wherein a thickness of the barrier layer is less than 25 Angstroms.
5 more elements
Dependencies are inferred from the claim text.