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US 9,287,370 B2Granted
Memory device comprising a transistor including an oxide semiconductor and semiconductor device including the same
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorYoshiyuki Kurokawa
Life of this patent
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Abstract
A memory device consumes low power, has high capacity, and is shared by a plurality of processors. A data write transistor of a memory device is manufactured with a material capable of achieving a sufficiently low off-state current of a transistor (e.g., an oxide semiconductor material that is a wide band gap semiconductor). The memory device has a memory cell including at least one data write transistor, at least one data storage transistor, and at least two data read transistors.
Claims16
A memory device comprising:
- a first transistor including a first channel formation region;
- a second transistor including a second channel formation region;
- a third transistor including a third channel formation region;
- a fourth transistor including a fourth channel formation region;
- a first line;
- a second line;
- a third line;
- a fourth line;
- a fifth line;
- a sixth line;
- and
- a seventh line,
- wherein one of a source and a drain of the first transistor is electrically connected to the first line,
- wherein one of a source and a drain of the second transistor is electrically connected to the second line,
- wherein one of a source and a drain of the third transistor is electrically connected to the third line,
- wherein one of a source and a drain of the fourth transistor is electrically connected to the fourth line,
- wherein a gate of the first transistor is electrically connected to the fifth line,
- wherein a gate of the third transistor is electrically connected to the sixth line,
- wherein a gate of the fourth transistor is electrically connected to the seventh line,
- wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor so that a node is formed,
- wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor,
- wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fourth transistor,
- wherein the first channel formation region includes a semiconductor material that is different from a semiconductor material in the second channel formation region, the third channel formation region and the fourth channel formation region, and
- wherein the first channel formation region includes an oxide semiconductor.
21 more elements
A memory device comprising:
- a first transistor including a first channel formation region;
- a second transistor including a second channel formation region;
- a third transistor including a third channel formation region;
- a fourth transistor including a fourth channel formation region;
- a fifth transistor including a fifth channel formation region;
- a first line;
- a second line;
- a third line;
- a fourth line;
- a fifth line;
- a sixth line;
- a seventh line;
- an eighth line;
- and
- a ninth line,
- wherein one of a source and a drain of the first transistor is electrically connected to the first line,
- wherein one of a source and a drain of the second transistor is electrically connected to the second line,
- wherein one of a source and a drain of the third transistor is electrically connected to the third line,
- wherein one of a source and a drain of the fourth transistor is electrically connected to the fourth line,
- wherein one of a source and a drain of the fifth transistor is electrically connected to the eighth line,
- wherein a gate of the first transistor is electrically connected to the fifth line,
- wherein a gate of the third transistor is electrically connected to the sixth line,
- wherein a gate of the fourth transistor is electrically connected to the seventh line,
- wherein a gate of the fifth transistor is electrically connected to the ninth line,
- wherein the other of the source and the drain of the first transistor and the other of the source and the drain of the fifth transistor are electrically connected to a gate of the second transistor so that a node is formed,
- wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor,
- wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fourth transistor,
- wherein the first channel formation region includes a semiconductor material different from a semiconductor material in the second channel formation region, the third channel formation region and the fourth channel formation region,
- wherein the first channel formation region includes an oxide semiconductor, and
- wherein the fifth channel formation region includes an oxide semiconductor.
27 more elements
Dependencies are inferred from the claim text.