CMOS multi-pinned (MP) pixel
AssigneeSRI International
InventorJames Robert Janesick
Life of this patent
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Abstract
A CMOS multi-pinned pixel having very low dark current and very high charge transfer performance over that of conventional CMOS pixels is disclosed. The CMOS pixel includes epitaxial silicon and at least one transfer gate formed upon the epitaxial silicon. A pinned-photodiode is formed in the epitaxial silicon. A multi-pinned (MP) implant layer is implanted in the epitaxial silicon at least partially extending across the pinned-photodiode and substantially underlying the at least one transfer gate of the CMOS pixel to promote dark current passivation during an accumulation state and promote charge transfer during a transfer state.
Claims29
A CMOS pixel, comprising:
- epitaxial silicon;
- at least one transfer gate formed overlying the epitaxial silicon;
- a pinned-photodiode formed in the epitaxial silicon adjacent to the at least one transfer gate;
- a multi-pinned (MP) implant layer implanted in the epitaxial silicon, wherein the pinned-photodiode comprises a portion of the MP implant layer and another portion of the MP implant layer is under the at least one transfer gate;
- and
- a sense node at least partially extending into the MP implant layer proximal to at least one of the at least one transfer gate.
A CMOS pixel, comprising:
- epitaxial silicon;
- at least one transfer gate formed overlying the epitaxial silicon;
- a pinned-photodiode formed in the epitaxial silicon adjacent to the at least one transfer gate;
- and
- a multi-pinned (MP) implant layer implanted in the epitaxial silicon, wherein the pinned-photodiode comprises a portion of the MP implant layer and another portion of the MP implant layer is under the at least one transfer gate, wherein the MP implant layer extends substantially across the entire CMOS pixel.
A method of fabricating a CMOS pixel comprising:
- implanting a multi-pinned (MP) implant layer into epitaxial silicon, wherein the implanting of the MP implant layer occurs substantially across the entire CMOS pixel;
- and
- forming a five transistor pinned-photodiode pixel into the epitaxial silicon, wherein the five transistor pinned-photodiode pixel comprises a pinned photo-diode and at least one transfer gate, wherein the MP implant layer provides a pinning potential to pin elements of the CMOS pixel at multiple locations, and wherein a portion of the MP implant layer is comprised in the pinned-photodiode and another portion of the MP implant layer is under the at least one transfer gate.
Dependencies are inferred from the claim text.