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US 9,287,313 B2Granted
Active pixel sensor having a raised source/drain
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhy-Jyi Sze
Life of this patent
Estimating the term…
Abstract
An integrated circuit having an array of APS cells. Each cell in the array has at least one transistor source or drain region that is raised relative to a channel region formed in a semiconductor substrate. The raised source or drain region includes doped polysilicon deposited on the surface of the semiconductor body and a region of the bodyextending to the channel region that has been doped to an opposite doping type from that of the channel region by diffusion of dopants from the deposited polysilicon.
Claims19
A device, comprising:
- an integrated circuit comprising an array of active pixel sensor cells formed on a semiconductor body;
- the active pixel sensor cells each having a transistor that has a channel region and a raised source or drain region;
- the channel region being a doped region of the semiconductor body;
- the raised source or drain region comprising doped polysilicon positioned over and in contact with the semiconductor body and a region of the semiconductor body that is doped to an opposite doping type of the channel region by diffusion of dopants into the semiconductor body from the doped polysilicon;
- and
- wherein the doped polysilicon of the raised source or drain region extends to overlay a gate of a source follower transistor of the active pixel sensor cells.
3 more elements
A transistor, comprising:
- a gate stack comprising a dielectric layer and a conductive layer positioned over a channel region of a semiconductor body;
- and
- a raised source or drain region disposed at a position laterally adjacent to the channel region, wherein the raised source or drain region is doped with an opposite doping type of the channel region;
- a sidewall spacer located between the gate stack and the raised source or drain region, wherein the sidewall spacer has a planar upper surface that is aligned with an upper surface of a hard mask layer overlying the conductive layer;
- and
- wherein the raised source or drain region are positioned over and in contact with an embedded source or drain region disposed within the semiconductor body.
3 more elements
A transistor, comprising:
- a dielectric layer positioned over a channel region of a semiconductor body;
- a conductive layer positioned over the dielectric layer;
- a nitride-containing hard mask layer positioned over the conductive layer;
- a raised source or drain region comprising doped polysilicon positioned over and in contact with a source or drain region of the semiconductor body, wherein the doped polysilicon of the raised source or drain region extends to overlay the nitride-containing hard mask layer;
- a sidewall spacer located between and in contact with both the conductive layer and the raised source or drain region;
- and
- a polysilicon gate contact positioned over and in contact with the conductive layer.
4 more elements
Dependencies are inferred from the claim text.