Imaging sensor structure and method

A method for fabricating a three dimensional (3D) image sensor structure, comprising:

• providing an image sensor substrate having image sensors formed therein and a first interconnect structure formed thereon, and a logic substrate having a logic circuit formed therein and a second interconnect structure formed thereon;
• bonding the logic substrate to the image sensor substrate in a configuration that the first interconnect structure and second interconnect structure are sandwiched between the logic substrate and the image sensor substrate;
• after bonding the logic substrate, thinning-down the logic substrate by performing a polishing process;
• and
• after performing the polishing process, performing an etching process, thereby forming a backend deep contact (BDCT) feature that continuously extends from the logic substrate, through a first metal line in the second interconnect structure and contacts a second metal line in the first interconnect structure, the BDCT feature being electrically coupling the logic circuit to the image sensors.

A method for fabricating a three dimensional (3D) image sensor structure, comprising:

• receiving a first semiconductor substrate having a plurality of imaging sensors and a first interconnect structure formed on the first semiconductor substrate;
• receiving a second semiconductor substrate having a logic circuit and a second interconnect structure formed on the second semiconductor substrate;
• forming a through-semiconductor via (TSV) feature in the second substrate, coupled to the second interconnect structure;
• bonding the first semiconductor substrate and the second semiconductor substrate together in a configuration such that the first interconnect structure and the second interconnect structure are sandwiched between the first semiconductor substrate and the second semiconductor substrate, wherein the TSV feature couples to the first interconnect structure, thereby electrically coupling the logic circuit to the image sensors, wherein the TSV feature extends from the second interconnect structure to the first interconnect structure in a first direction;
• performing a polishing process to thin-down the second semiconductor substrate;
• and
• forming a conductive feature in the second interconnection structure, the conductive feature contacting the TSV feature.