Semiconductor device and method for controlling semiconductor device

A semiconductor device comprising:

• a semiconductor support substrate;
• an insulation layer formed on said semiconductor support substrate and having a thickness of at most 10 nm;
• a semiconductor layer formed on said insulation film;
• a logic circuit comprising a first field-effect transistor arranged in an upper surface of said semiconductor layer, and including a first gate electrode and first source and drain regions of a second conductivity type;
• and
• a memory circuit comprising a second field-effect transistor arranged in the upper surface of said semiconductor layer, electrically insulated from said first field-effect transistor by an element separation film arranged in a surface of said semiconductor layer, and including a second gate electrode and second source and drain regions of the second conductivity type, wherein
• the semiconductor support substrate of a first conductivity type includes, underneath the first field-effect transistor bounded by the element separation film, a part of the semiconductor support substrate of the first conductivity type, a first impurity region of the second conductivity type, and a second impurity region of the first conductivity type arranged in said first impurity region, and includes, direct underneath the first gate electrode of the first field-effect transistor, a third impurity region of the first conductivity type between the second impurity region and the insulation layer for adjusting a threshold voltage of the first field-effect transistor, the first and third impurity regions being physically separated from each other, the part of the semiconductor support substrate, the first impurity region, the second impurity region, and the third impurity region being arranged in that order toward the insulation layer, the first conductivity type being different from the second conductivity type,
• the semiconductor support substrate of the first conductivity type further includes, underneath the second field-effect transistor bounded by the element separation film, another part of the semiconductor support substrate of the first conductivity type, a fourth impurity region of the second conductivity type, a fifth impurity region of the first impurity type in the fourth impurity region, and a sixth impurity region of the first impurity type between the fifth impurity region and the insulation layer for adjusting a threshold voltage of the second field-effect transistor, the another part of the semiconductor support substrate, the fourth impurity region, the fifth impurity region, and the sixth impurity region being arranged in that order toward the insulation layer,
• the semiconductor support substrate of the first conductivity type further includes seventh impurity regions of the second conductivity type disposed directly underneath the first source and drain regions, respectively, and between the second impurity layer and the insulation layer, the third impurity region being disposed between the seventh impurity regions, and
• an impurity concentration of the sixth impurity region is less than that of the third impurity region.