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US 9,287,286 B2Granted
Three-dimensional nonvolatile memory device, semiconductor system including the same, and method of manufacturing the same
AssigneeSK hynix Inc.
InventorsTae Kyung Kim, Dae Sung Eom
Life of this patent
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Abstract
A three-dimensional nonvolatile memory device includes a first vertical channel layer and a second vertical channel layer extending from a substrate, a plurality of memory cells, first selection transistors and second selection transistors spaced apart from each other along the first vertical channel layer and the second vertical channel layer, a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, and a common source line formed over the second vertical channel layer.
Claims13
A three-dimensional nonvolatile memory device, comprising:
- a plurality of word lines stacked over a substrate;
- a first vertical hole and a second vertical hole vertically passing through the word lines;
- a first vertical channel layer formed in the first vertical hole;
- a second vertical channel layer formed in the second vertical hole, wherein the second vertical channel layer is coupled to the first vertical channel layer through a pipe channel layer;
- tunnel insulating layers, charge trap layers and charge blocking layers surrounding the first vertical channel layer and the second vertical channel layer in each of the first vertical hole and the second vertical hole;
- a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, wherein the pad and the contact plug are vertically in alignment with the first vertical channel layer, and a width of the pad is greater than that of the first vertical hole and that of the contact plug;
- and
- a common source line formed over the second vertical channel layer.
5 more elements
A semiconductor system, comprising:
- a three-dimensional nonvolatile memory device comprising:
- a plurality of word lines stacked over a substrate;
- a first vertical hole and a second vertical hole vertically passing through the word lines;
- a first vertical channel layer formed in the first vertical hole;
- a second vertical channel layer formed in the second vertical hole, wherein the second vertical channel layer is coupled to the first vertical channel layer through a pipe channel layer;
- tunnel insulating layers, charge trap layers and charge blocking layers surrounding the first vertical channel layer and the second vertical channel layer in each of the first vertical hole and the second vertical hole;
- a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, wherein the pad and the contact plug are vertically in alignment with the first vertical channel layer, and a width of the pad is greater than that of the first vertical hole and that of the contact plug;
- and
- a common source line formed over the second vertical channel layer;
- and
- a memory controller configured to control at least one operation of the three-dimensional nonvolatile memory device.
8 more elements
Dependencies are inferred from the claim text.