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US 9,287,285 B2Granted
Self-aligned liner method of avoiding PL gate damage
AssigneeMacronix International Co., Ltd.
InventorsFang-Hao Hsu, Zusing Yang, Hong-Ji Lee
Life of this patent
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Abstract
A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.
Claims18
A semiconductor structure, comprising:
- a substrate;
- a first memory cell and a second memory cell formed above a side of the substrate;
- and
- a T-shape trench in the substrate between the first memory cell and the second memory cell;
- wherein the trench is disposed a first distance from the first memory cell and a second distance from the second memory cell, extends a depth into the substrate, and is characterized by one or more of (i) a width less than or about equal to the first distance, (ii) a width less than or about equal to the second distance, and (iii) a width less than or about equal to a sum of the first distance and the second distance,
- wherein the T-shape comprises a center with opposing arms and a stem extending outwardly therefrom, the arms extending away from the center in directions parallel to the side and corresponding geometrically to the first distance and the second distance, and the stem extending in a direction transverse to the side into the substrate and corresponding geometrically to the trench, whereby a T-shape results from the relative shapes and orientations of the first distance, the second distance and the trench.
3 more elements
A semiconductor structure comprising:
- a substrate;
- a plurality of first features of a first silicon layer disposed above a side of the substrate and insulated therefrom by an insulator layer;
- a plurality of second features of a second silicon layer disposed above the first features, the second features being insulated from the first features;
- a first liner layer disposed over the semiconductor structure;
- and
- a second liner layer disposed over the first liner layer, whereby the second liner layer is constructed with a first width at an upper portion of the second features and with a second width at a lower portion of the first features, the first and second widths being measured in a direction parallel to the side and the second width being less than the first width.
3 more elements
A semiconductor structure comprising:
- a plurality of first features of a first silicon layer disposed above a side of a substrate and insulated therefrom by an insulator layer;
- and
- a plurality of second features of a second silicon layer disposed above the first features, the second features being insulated from the first features;
- and
- a first liner layer disposed over the semiconductor structure, and a second liner layer disposed over the first liner layer, whereby the second liner layer is constructed with a first thickness on tops of the second features and with a second thickness at bottoms of and between the first features, the first and second thicknesses being measured in a direction normal to the side and the second thickness being less than the first thickness.
2 more elements
Dependencies are inferred from the claim text.