Method of forming a logic compatible flash memory

A method comprising:

• forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region of a semiconductor substrate;
• forming a dielectric protection layer comprising a first portion overlapping the first pad oxide layer and a second portion overlapping the second pad oxide layer;
• forming an etching mask to cover the first portion of the dielectric protection layer;
• removing the second portion of the dielectric protection layer and the second pad oxide layer;
• removing the etching mask;
• forming a floating gate dielectric over the second active region;
• forming a floating gate layer, wherein the floating gate layer comprises a first portion over the first portion of the dielectric protection layer, and a second portion over the floating gate dielectric;
• and
• performing a planarization on the first portion and the second portion of the floating gate layer, wherein after the planarization, the first portion of the floating gate layer is fully removed, and the first portion of the dielectric protection layer is exposed.

A method comprising:

• forming a dielectric protection layer over a semiconductor substrate, wherein the dielectric protection layer comprises:
• a first portion overlapping a first active region of the semiconductor substrate;
• a second portion overlapping a second active region of the semiconductor substrate;
• and
• a third portion overlapping a Shallow Trench Isolation (STI) region, with the STI region having an edge contacting an edge of the first active region;
• removing the second portion of the dielectric protection layer;
• forming a floating gate dielectric over the second active region;
• forming a floating gate layer comprising:
• a first portion overlapping the first portion of the dielectric protection layer;
• a second portion overlapping the floating gate dielectric;
• and
• a third portion overlapping the third portion of the dielectric protection layer;
• performing a planarization on the floating gate layer, wherein after the planarization, the first portion of the floating gate layer is removed, the second portion of the floating gate layer is thinned, and the third portion of the floating gate layer has a residue remaining;
• patterning the floating gate layer to form a floating gate over the second active region;
• and
• removing the residue.