Method to improve memory cell erasure

A method of manufacturing a semiconductor structure of a split gate flash memory cell, said method comprising:

• receiving a semiconductor substrate;
• forming over the semiconductor substrate a floating gate including a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on first opposing sides, respectively, of the floating gate;
• and
• forming a word line and an erase gate on second opposing sides of the floating gate.

A semiconductor structure of split gate flash memory cells, said semiconductor structure comprising:

• a semiconductor substrate including a first pair of source/drain regions, a second pair of source/drain regions, and an isolation region arranged between the first and second pairs of source/drain regions;
• a first erase gate located over a source/drain region of the first pair;
• a first word line and a first floating gate located over the semiconductor substrate between the source/drain regions of the first pair, wherein the first floating gate is arranged between the first word line and the first erase gate, and wherein the first floating gate includes a pair of protrusions extending vertically up from a top surface of the first floating gate and arranged on opposing sides, respectively, of the first floating gate;
• a second erase gate located over a source/drain region of the second pair;
• and
• a second word line and a second floating gate located over the semiconductor substrate between the source/drain regions of the second pair, wherein the second floating gate is arranged between the second word line and the second erase gate, and wherein the second floating gate includes a pair of protrusions extending vertically up from a top surface of the second floating gate and arranged on opposing sides, respectively, of the second floating gate;
• wherein one of the opposing sides of each floating gate faces the isolation region.