Silicon nitride (SiN) encapsulating layer for silicon nanocrystal memory storage

A memory device, comprising:

• a select gate formed over a surface of a semiconductor substrate between source and drain regions that are laterally separated by a channel region formed beneath the select gate;
• a control gate formed along a portion of a sidewall of the select gate and over the surface of the semiconductor between the select gate and the source and drain regions, wherein a sidewall spacer is disposed along a sidewall of the control gate;
• and
• a charge-trapping layer having a sidewall aligned with an outer sidewall of the sidewall spacer, which separates the control gate from the select gate, comprising:
• a tunneling oxide layer formed along surfaces of the select gate and the surface of the semiconductor substrate between the select gate and the source and drain regions;
• a plurality of nanocrystals formed along a surface of the tunneling oxide layer along a lower portion of a sidewall of the select gate that faces the source region, and over the tunneling oxide layer between the select gate and source region, and configured to store different amounts of charge depending on what bias is applied over the select and the control gates;
• an insulating encapsulating layer which embeds the nanocrystals, and which is isolated from the select gate by the tunneling oxide layer;
• and
• a control oxide layer formed along a surface the encapsulating layer, which isolates the encapsulating layer from the control gate.

A memory device, comprising:

• a select gate disposed over a semiconductor substrate between a source region and a drain region that are laterally separated by a channel region formed beneath the select gate;
• a “L” shaped control gate comprising a vertical portion disposed along a lower sidewall of the select gate and a lateral portion extended along a surface of the semiconductor substrate between the select gate and the source region;
• and
• a charge-trapping layer, which separates the control gate from the select gate and extends under the control gate, comprising:
• a tunneling dielectric layer disposed along a first sidewall surface of the select gate facing the drain region, disposed along a second sidewall surface of the select gate facing the source region and extending continuously under the control gate;
• a plurality of nanocrystals disposed along a lower portion of a sidewall surface of the tunneling dielectric layer facing the source region and extending under the control gate;
• an encapsulating layer filling spaces between adjacent nanocrystals;
• and
• a control dielectric layer formed along a surface the encapsulating layer;
• wherein the encapsulating layer extends over the plurality of nanocrystals and separates the nanocrystals from the control dielectric layer;
• wherein the control dielectric layer has an upper surface aligned with a planar upper surface of the control gate.