Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices

A method of forming a plurality of vertical transistor devices;

• individual devices comprising an outer source/drain region, an inner source/drain region, and a channel region each formed within an active area;
• a plurality of gate line pairs on opposing sides of multiple channel regions;
• a plurality of buried data/sense lines angling beneath the gate line pairs;
• the inner source/drain regions individual electrically coupling to individual buried data/sense lines, the method comprising:
• forming lines of active area alternating with lines of dielectric isolation within a semiconductor substrate;
• etching buried data/sense line trenches into the lines of active area and lines of dielectric isolation, the buried data/sense line trenches angling obliquely relative to the lines of active area and the lines of dielectric isolation, individual lines of dielectric isolation underlying multiple buried data/sense line trenches;
• forming the data/sense lines within the buried data/sense line trenches;
• etching gate line trenches into the semiconductor substrate, the gate line trenches angling obliquely relative to the lines of active area and the lines of dielectric isolation and bifurcating the active area between two immediately adjacent data/sense lines;
• forming the conductive gate line pairs within the gate line trenches;
• and
• forming the outer and inner source/drain regions and the channel regions within the active area.