Semiconductor memory device and method for manufacturing the same

A semiconductor device comprising:

• a first conductive layer;
• a first insulating layer over the first conductive layer;
• contact plugs in the first insulating layer;
• a second insulating layer over the contact plugs, and over and in direct contact with the first insulating layer;
• a second conductive layer over and in contact with a top surface of the second insulating layer;
• an oxide semiconductor layer over and in contact with the second conductive layer and the contact plugs;
• a third insulating layer adjacent to the second insulating layer with the oxide semiconductor layer interposed therebetween;
• a third conductive layer adjacent to a first side surface of the second insulating layer with the oxide semiconductor layer and the third insulating layer interposed therebetween;
• and
• a fourth conductive layer adjacent to a second side surface of the second insulating layer with the oxide semiconductor layer and the third insulating layer interposed therebetween,
• wherein the oxide semiconductor layer includes a channel formation region,
• wherein the oxide semiconductor layer is electrically connected to the first conductive layer, and
• wherein a thickness of each of the third conductive layer and the fourth conductive layer is greater than or equal to 40% and less than or equal to 80% of a sum of thicknesses of the second insulating layer and the second conductive layer.

A semiconductor device comprising:

• a first conductive layer;
• a first insulating layer over the first conductive layer;
• contact plugs in the first insulating layer;
• a second insulating layer over the contact plugs, and over and in direct contact with the first insulating layer;
• a second conductive layer over and in contact with a top surface of the second insulating layer;
• an oxide semiconductor layer over and in contact with the second conductive layer and the contact plugs;
• a third insulating layer adjacent to the second insulating layer with the oxide semiconductor layer interposed therebetween;
• and
• a third conductive layer adjacent to a side surface of the second insulating layer with the oxide semiconductor layer and the third insulating layer interposed therebetween,
• wherein the oxide semiconductor layer includes a channel formation region,
• wherein the oxide semiconductor layer is electrically connected to the first conductive layer, and
• wherein a thickness of the third conductive layer is greater than or equal to 40% and less than or equal to 80% of a sum of thicknesses of the second insulating layer and the second conductive layer.