US 9,287,260 B1 · Transistors having one or more dummy lines with different collective widths coupled thereto

Abstract

In an embodiment, an array of transistors has a first line coupled to a first transistor. The first line extends over a second transistor that is successively adjacent to the first transistor and over a third transistor that is successively adjacent to the second transistor. A second line is coupled to the second transistor and extends over the third transistor. One or more first dummy lines are coupled to the first line and extend from the first transistor to the second transistor. One or more second dummy lines are coupled to the second line and extend from the second transistor to the third transistor. A collective width of the one or more first dummy lines is greater than a collective width of the one or more second dummy lines.

Claims25

Dependent claims

An array of transistors, comprising:

a first line coupled to a first transistor, the first line extending over a second transistor that is successively adjacent to the first transistor and over a third transistor that is successively adjacent to the second transistor;
a second line coupled to the second transistor and extending over the third transistor;
one or more first dummy lines coupled to the first line and extending from the first transistor to the second transistor;
and
one or more second dummy lines coupled to the second line and extending from the second transistor to the third transistor;
wherein a collective width of the one or more first dummy lines is greater than a collective width of the one or more second dummy lines.

3 more elements

An array of transistors, comprising:

a plurality of successively adjacent transistors commonly coupled to a control line, each of the plurality of successively adjacent transistors coupled to a respective runner by a respective line that is transverse to its respective runner, the respective runners being successively adjacent to each other;
and
different numbers of dummy runners respectively between different respective pairs of the respective lines, the respective lines of each of the different respective pairs respectively coupled to successively adjacent transistors of a respective pair of successively adjacent transistors;
wherein the number of dummy runners between each pair of the different respective pairs of the respective lines is coupled to one of the respective lines of that respective pair and is electrically isolated from the other one of the respective lines of that respective pair.

1 more element

Dependencies are inferred from the claim text.

Transistors having one or more dummy lines with different collective widths coupled thereto

Life of this patent

Transistors having one or more dummy lines with different collective widths coupled thereto

Life of this patent

Abstract

Claims25