Power gating for three dimensional integrated circuits (3DIC)

A three dimensional integrated circuit (3DIC) structure in a semiconductor die comprising:

• a first power gating cell (PGC) formed on a first active device layer;
• a first interconnect structure formed over the first active device layer, wherein the first interconnect structure connects the first PGC to a power source;
• a dielectric material insulating the first interconnect structure;
• a first virtual power circuit formed on a second active device layer, wherein the first active device layer and the second active device layer are on separate levels;
• and
• a second interconnect structure formed between the first PGC and the first virtual power circuit, wherein the second interconnect structure electrically connects the first PGC and the first virtual power circuit.

A three dimensional integrated circuit (3DIC) structure comprising:

• a first power gating cell (PGC) on a first active device layer;
• a first interconnect structure over the first PGC, the first interconnect structure connecting the first PGC to a power source;
• a first virtual power circuit on a second active device layer, the second active device layer being on a different level from the first active device layer;
• a second interconnect structure formed between the first PGC and the first virtual power circuit;
• and
• a conductive path between the first PGC and the second interconnect structure.