Electronic device and protection circuit
AssigneeSTMicroelectronics S.r.l.
InventorsJean Jimenez, Boris Heitz, Johan Bourgeat
Life of this patent
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Abstract
An electronic device includes a first device terminal and a second device terminal. A first and a second thyristor are reverse-connected between the two device terminals. A first and a second MOS transistor are respectively coupled between the conduction electrodes (emitters and collectors) of the two NPN transistors of the two thyristors. A third MOS transistor is coupled between the emitters of the two NPN bipolar transistors of the two thyristors and a fourth MOS transistor is coupled between the bases of the two PNP bipolar transistors of the two thyristors. A gate region is common to all the MOS transistors and a semiconductor substrate region includes the substrates of all the MOS transistors.
Claims20
An electronic device, comprising:
- a first device terminal;
- a second device terminal;
- a first thyristor and a second thyristor reverse-connected between the first and second device terminals, each thyristor including an anode, a cathode, an NPN bipolar transistor and a PNP bipolar transistor, each bipolar transistor having an emitter, a base, and a collector;
- a first MOS transistor and a second MOS transistor coupled between conduction electrodes of the NPN bipolar transistors of the first and second thyristors;
- a third MOS transistor coupled between emitters of the NPN bipolar transistors of the first and second thyristors;
- a fourth MOS transistor coupled between bases of the PNP bipolar transistors of the first and second thyristors;
- a gate region common to the first, second, third and fourth MOS transistors;
- and
- a common semiconductor region, wherein the first, second, third and fourth MOS transistors are formed within the common semiconductor region.
A circuit, comprising:
- electronic circuitry to be protected from ESD, the electronic circuitry comprising a first circuit terminal and a second circuit terminal;
- a first thyristor and a second thyristor reverse-connected between the first and second circuit terminals, each thyristor including an anode, a cathode, an NPN bipolar transistor and a PNP bipolar transistor, each bipolar transistor having an emitter, a base, and a collector;
- a first MOS transistor and a second MOS transistor coupled between conduction electrodes of the NPN bipolar transistors of the first and second thyristors;
- a third MOS transistor coupled between emitters of the NPN bipolar transistors of the first and second thyristors;
- a fourth MOS transistor coupled between bases of the PNP bipolar transistors of the first and second thyristors;
- a common gate region common to the first, second, third and fourth MOS transistors;
- and
- a common semiconductor region, wherein the first, second, third and fourth MOS transistors are formed within the common semiconductor region.
An input/output cell of an integrated circuit, comprising:
- an input/output lug;
- a first power supply terminal;
- a second power supply terminal;
- a first protection circuit having first and second circuit terminals coupled between the first power supply terminal and the input/output lug;
- a second protection circuit having first and second circuit terminals coupled between the input/output lug and the second power supply terminal;
- and
- a third protection circuit having first and second circuit terminals coupled between the first power supply terminal and the second power supply terminal;
- wherein the first, second, and third protection circuits each comprise:
- a first thyristor and a second thyristor reverse-connected between the first and second circuit terminals, each thyristor including an anode, a cathode, an NPN bipolar transistor and a PNP bipolar transistor, each bipolar transistor having an emitter, a base, and a collector;
- a first MOS transistor and a second MOS transistor coupled between conduction electrodes of the NPN bipolar transistors of the first and second thyristors;
- a third MOS transistor coupled between emitters of the NPN bipolar transistors of the first and second thyristors;
- a fourth MOS transistor coupled between bases of the PNP bipolar transistors of the first and second thyristors;
- a common gate region common to the first, second, third and fourth MOS transistors;
- and
- a common semiconductor region, wherein the first, second, third and fourth MOS transistors are formed within the common semiconductor region.
Dependencies are inferred from the claim text.