Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device, the method comprising:

• forming a first insulating interlayer on a first substrate, the first insulating interlayer containing a first conductive pattern structure therein;
• sequentially forming a first etch stop layer and a second insulating interlayer on the first insulating interlayer to cover the first conductive pattern structure;
• forming a first opening through the second insulating interlayer and the first etch stop layer to expose a top surface of the first conductive pattern structure;
• forming a first diffusion prevention insulation layer on an inner wall of the first opening and on the second insulating interlayer;
• anisotropically etching the first diffusion prevention insulation layer to form a first diffusion prevention insulation pattern on the inner wall of the first opening;
• forming a second conductive pattern structure in the first opening having the first diffusion prevention insulation pattern therein, the second conductive pattern structure having a planarized top surface;
• forming a third insulating interlayer on a second substrate, the third insulating interlayer containing a third conductive pattern structure therein;
• sequentially forming a second etch stop layer and a fourth insulating interlayer on the third insulating interlayer to cover the third conductive pattern structure;
• forming a second opening through the fourth insulating interlayer and the second etch stop layer to expose a top surface of the third conductive pattern structure;
• forming a second diffusion prevention insulation layer on an inner wall of the second opening and on the fourth insulating interlayer;
• anisotropically etching the second diffusion prevention insulation layer to form a second diffusion prevention insulation pattern on the inner wall of the second opening;
• forming a fourth conductive pattern structure in the second opening in which the second diffusion prevention insulation pattern is formed, the fourth conductive pattern structure having a planarized top surface;
• performing a plasma treatment process on at least one of the first and second substrates provided with the second and fourth conductive pattern structures thereon, respectively;
• and
• contacting the second and fourth conductive pattern structures to each other to bond the first and second substrates.

A method of manufacturing a semiconductor device, the method comprising:

• forming a first stacked structure having a planarized surface and comprising a first substrate, a first insulating interlayer on the first substrate, a first conductive pattern structure within the first insulating interlayer and having a surface coplanar with a surface of the first insulating interlayer, and a first diffusion prevention insulation pattern within the first insulating interlayer and adjacent to the first conductive pattern structure, the first diffusion prevention insulation pattern having a surface coplanar with the surface of the first insulating interlayer;
• forming a second stacked structure having a planarized surface and comprising a second substrate, a second insulating interlayer on the second substrate, a second conductive pattern structure within the second insulating interlayer and having a surface coplanar with a surface of the second insulating interlayer, and a second diffusion prevention insulation pattern within the second insulating interlayer and adjacent to the second conductive pattern structure, the second diffusion prevention insulation pattern having a surface coplanar with the surface of the second insulating interlayer;
• performing a plasma treatment on at least one of the surfaces of the first and the second stacked structures;
• disposing the surface of the first stacked structure on the surface of the second stacked structure such that the first conductive pattern structure is in contact with the second conductive pattern structure, but the first conductive pattern structure is not in contact with the second insulating interlayer and the second conductive pattern structure is not in contact with the first insulating interlayer;
• and
• bonding the first stacked structure to the second stacked structure.