US 9,287,248 B2Granted

Embedded memory and power management subpackage

AssigneeIntel Corporation

InventorsJohn S. Guzek, Debendra Mallik, Sasha N. Oster, Timothy E. McIntosh

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Abstract

Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.

Claims20

Dependent claims

A package assembly comprising:

a subpackage having a first side and a second side disposed opposite to the first side, the subpackage including:
one or more package-level interconnect contacts disposed on the first side the subpackage;
and
a first die having a first side and a second side disposed opposite to the first side, the first side of the first die being disposed between the second side of the first die and the first side of the subpackage;
and
a second die having a first side and a second side disposed opposite to the first side, the first side of the second die being coupled to the second side of the subpackage and electrically coupled to the second side of the first die, wherein a first portion of the first die is within an area defined b extension of a perimeter of the second die in a direction perpendicular to the first side of the second die, wherein a second portion of the first die extends outside of the area defined by the extension of the perimeter of the second die in the direction perpendicular to the first side of the second die, wherein the subpackage includes one or more conductive pathways located between the second side of the first die and the second side of the subpackage, and wherein the one or more conductive pathways are coupled to the second portion of the first die that extends outside of the area defined by the extension of the perimeter of the second die in the direction perpendicular to the first side of the second die.

3 more elements

A computing device comprising:

a circuit board;
a subpackage having a first side and a second side disposed opposite to the first side, the first side being coupled with the circuit board using one or more package-level interconnects disposed on the first side of the subpackage, the subpackage including:
a first die having a first side and a second side disposed opposite to the first side, the first side of the first die being disposed between the second side of the first die and the first side of the subpackage;
and
a second die having a first side and a second side disposed opposite to the first side, the first side of the second die being coupled to the second side of the subpackage and electrically coupled to the second side of the first die, wherein a first portion of the first die is within an area defined b extension of a perimeter of the second die in a direction perpendicular to the first side of the second die, wherein a second portion of the first die extends outside of the area, wherein the subpackage includes one or more conductive pathways located between the second side of the first die and the second side of the subpackage, and wherein the one or more conductive pathways are coupled to the second portion of the first die.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/104,877Filed 12 Dec 2013
Published: US 2015/0171065 A118 Jun 2015
Granted: 15 Mar 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification21 codes

H10W 90/00
Package configurations
H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10W 40/22
Arrangements for cooling: characterised by their shape, e.g. having conical or cylindrical projections
H10W 70/09
By depositing layers on the chip or wafer, e.g. "chip-first" RDLs: extending onto an encapsulation that laterally surrounds the chip or wafer,…