Techniques for interconnecting stacked dies using connection sites

An integrated circuit die, comprising:

• conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof;
• a first core circuit located outside the contiguous region;
• and
• alignment circuitry configurable to couple a first subset of the connection sites to the first core circuit and to decouple a second subset of the connection sites from the first core circuit, the alignment circuitry additionally configurable to decouple the second subset of the connection sites from every core circuit on the integrated circuit die.

An integrated circuit die, comprising:

• conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof;
• a first core circuit located outside the contiguous region;
• a second core circuit;
• and
• alignment circuitry configurable to couple a first subset of the connection sites to the first core circuit and to decouple a second subset of the connection sites from the first core circuit, the alignment circuitry additionally configurable to couple the first subset of the connection sites to the second core circuit and to couple the second subset of the connection sites to the first core circuit.

An integrated circuit die, comprising:

• connection sites located at least on a surface of the integrated circuit die;
• a first core circuit;
• a second core circuit;
• and
• alignment circuitry configurable to couple the first core circuit to a first one of the connection sites and the second core circuit to a second one of the connection sites in a first alignment configuration, wherein the alignment circuitry is additionally configurable to couple the first core circuit to the second one of the connection sites and the second core circuit to the first one of the connection sites in a second alignment configuration, and wherein the connection sites are all located within a contiguous region overlapping none of the first core circuit, the second core circuit and the alignment circuitry.

A method comprising:

• configuring alignment circuitry on an integrated circuit die according to a first alignment configuration;
• transmitting signals through the alignment circuitry configured according to the first alignment configuration between a first core circuit in the integrated circuit die and a first connection site on the integrated circuit die;
• configuring the alignment circuitry according to a second alignment configuration;
• and
• transmitting signals through the alignment circuitry configured according to the second alignment configuration between the first core circuit and a second connection site on the integrated circuit die.