Adhesive pattern for advance package reliability improvement

An integrated chip (IC) package, comprising:

• an integrated chip (IC) die coupled to a substrate by a plurality of electrically conductive bonding structures disposed within an underfill layer configured to prevent CTE mismatch between the IC die and the substrate;
• a first adhesive layer having a first Young's modulus and disposed onto the substrate at a first plurality of positions, which are laterally located between a side of the substrate and a proximate side of the IC die;
• and;
• a second adhesive layer having a second Young's modulus less than the first Young's modulus and disposed onto the substrate at a second plurality of positions, which are laterally located between a corner of the substrate and a proximate corner of the IC die;
• a lid affixed to the substrate by the first and second adhesive layers and configured to extend to a position overlying the IC die;
• and
• a thermal interface material (TIM) layer vertically disposed between the IC die and the lid, wherein the TIM layer and the first or second adhesive layers comprise a same material.

A method of forming an integrated chip (IC) package, comprising:

• bonding an integrated chip (IC) die is to a substrate using an electrically conductive bonding structure disposed within an underfill layer configured to prevent CTE mismatch between the IC die and the substrate;
• selectively depositing a first adhesive layer onto the substrate at a first plurality of positions surrounding the IC die;
• selectively depositing a second adhesive layer, having a second Young's modulus that is less than a first Young's modulus of the first adhesive layer, onto the substrate at a second plurality of positions surrounding the IC die, wherein the second adhesive layer has an ‘L’ shape comprising two connected orthogonal legs separated from the first adhesive layer by spaces having different sizes;
• and
• bringing a lid into contact with the first and second adhesive layers.