Methods for forming conductive vias in semiconductor device components
AssigneeMicron Technology, Inc.
InventorNishant Sinha
Life of this patent
Estimating the term…
Abstract
A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer, may be formed on surfaces of each hole. Surfaces within each hole may be coated with a seed layer, which facilitates adhesion of conductive material within each hole. Conductive material is introduced into each hole. Introduction of the conductive material may be effected by deposition or plating. Alternatively, conductive material in the form of solder may be introduced into each hole.
Claims20
A method for forming a conductive interconnect in a substrate, comprising:
- forming at least one blind via in a first surface of a substrate, the at least one blind via extending toward an opposite, second surface of the substrate;
- forming a dielectric material on each of the first surface of the substrate and surfaces of the at least one blind via;
- forming a conductive seed material over the dielectric material;
- completely removing the conductive seed material and the dielectric material overlying the first surface of the substrate while substantially retaining the conductive seed material and the dielectric material within the at least one blind via;
- forming conductive material on the substantially retained conductive seed material to fill a remaining space within the at least one blind via;
- and
- performing a removal process to the second surface of the substrate to expose the conductive material within the at least one blind via.
A method for forming a conductive interconnect in a substrate, comprising:
- forming at least one via in a substrate, the at least one via extending from a first surface of the substrate to an opposite, second surface of the substrate;
- lining surfaces of the at least one via with a dielectric material;
- forming a conductive seed material over each of the first surface of the substrate, the opposite, second surface of the substrate, and the dielectric material lining the at least one via;
- completely removing the conductive seed material over each of the first surface of the substrate and the opposite, second surface of the substrate while substantially retaining the conductive seed material in the at least one via;
- and
- forming conductive material on the substantially retained conductive seed material to fill a remaining space within the at least one via.
A method for forming a conductive interconnect in a substrate, comprising:
- forming at least one blind via in a first surface of a substrate, the at least one blind via extending toward an opposite, second surface of the substrate;
- lining each of the first surface of the substrate and surfaces of the at least one blind via with an oxide material;
- forming a conductive material comprising tantalum on the oxide material;
- completely removing the conductive material and the oxide material overlying the first surface of the substrate while substantially retaining the conductive material and the oxide material within the at least one blind via;
- filling a remaining space within the at least one blind via with at least one other conductive material comprising copper such that the conductive material substantially circumscribes the at least one other conductive material;
- and
- performing an abrasive planarization process to the opposite, second surface of the substrate to expose the at least one other conductive material within the at least one blind via.
Dependencies are inferred from the claim text.