Resonant clocking for three-dimensional stacked devices

A memory device including:

• a plurality of die layers including a memory stack of a plurality of memory die layers including at least a first die layer and an adjacent second die layer, each die layer, including an active metal side and an opposite RDL (re-distribution layer), and a system die layer coupled with the memory stack, a plurality of through silicon vias including a first set of through silicon vias formed through the first die layer and a second set of through silicon vias formed through the second die layer;
• and
• a resonant clock network including a plurality of resonant circuits to carry clock signals, each of the resonant circuits including:
• a first through silicon via of the first set of through silicon vias, each first through silicon via including an inductive structure, the first through silicon via being used as an inductive circuit element to provide inductance for the resonant circuit, and
• a second through silicon via of the second set of through silicon vias, each second through silicon via including a capacitive structure, the second through silicon via being used as a capacitive circuit element of the resonant circuit, the first through silicon via of each resonant circuit being coupled with the respective second through silicon via of the resonant circuit via the RDL of the first die layer;
• wherein each of the first set of through silicon vias is utilized both for transport of the clock signals between die layers, including transport of clock signals from the first die layer to the second die layer, and for the generation of inductance for the respective resonant circuit;
• and
• wherein each of the resonant circuits is shared between the first die layer and the second die layer, a clock grid of the first die layer resonating at a same frequency and being synchronous with a clock grid of the second die layer.

A system comprising:

• a processor to process data;
• a transmitter or receiver for transmission of data;
• and
• a memory to store data, the memory providing for resonant clocking, the memory including:
• a clock driver to provide a clock signal,
• a plurality of die layers including a memory stack of a plurality of memory die layers including at least a first die layer and an adjacent second die layer, each die layer, including an active metal side and an opposite RDL (re-distribution layer), and a system die layer coupled with the memory stack, a plurality of through silicon vias including a first set of through silicon vias formed through the first die layer and a second set of through silicon vias formed through the second die layer, and
• a resonant clock network including a plurality of LC tank circuits to carry clock signals, each of the LC tank circuits including:
• a first through silicon via of the first set of through silicon vias, each first through silicon via including an inductive structure, the first through silicon via being using as an inductive circuit element to provide inductance for the LC tank circuit, and
• a second through silicon via of the second set of through silicon vias, each second through silicon via including a capacitive structure, the second through silicon via being used as a capacitive circuit element of the LC tank circuit, the first through silicon via of each LC tank circuit being coupled with the respective second through silicon via of the LC tank circuit via the RDL of the first die layer;
• wherein each of the first set of through silicon vias is utilized both for transport of the clock signals between die layers, including transport of clock signals from the first die layer to the second die layer, and for the generation of inductance for the respective LC tank circuit;
• and
• wherein each of the LC tank circuits is shared between the first die layer and the second die layer, a clock grid of the first die layer resonating at a same frequency and being synchronous with a clock grid of the second die layer.

A computer chip comprising:

• a first silicon die and a second silicon die, each silicon die including an active metal side and an opposite RDL (re-distribution layer);
• and
• a plurality of through silicon vias including a first set of through silicon vias formed through the first silicon die and a second set of through silicon vias formed through the second silicon die, wherein each of the first set of through silicon vias includes an inductive structure and each of the second set of through silicon vias includes a capacitive structure;
• wherein the computer chip includes a plurality of resonant circuits to carry clock signals, each of the resonant circuits including a first through silicon via of the first set of through silicon vias used as an inductive circuit element of the resonant circuit and a second through silicon via of the second set of through silicon vias used as a capacitive circuit element of the resonant circuit, the first through silicon via of each resonant circuit being coupled with the respective second through silicon via of the resonant circuit via the RDL of the first silicon die;
• wherein each of the first set of through silicon vias is utilized both for transport of the clock signals between silicon dies, including transport of clock signals from the first silicon die to the second silicon die, and for the generation of inductance for the respective resonant circuit;
• wherein the resonant circuit is resonant with a frequency of a clock signal that is driven on the computer chip;
• and
• wherein each of the resonant circuits is shared between the first die layer and the second die layer, a clock grid of the first die layer resonating at a same frequency and being synchronous with a clock grid of the second die layer.