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US 9,287,194 B2Granted
Packaging devices and methods for semiconductor devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorWensen Hung
Life of this patent
Estimating the term…
Abstract
Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging substrate including a semiconductor device mounting region. The packaging device includes a stress isolation structure (SIS) disposed on the packaging substrate proximate a portion of a perimeter of the semiconductor device mounting region.
Claims20
A packaging device for a semiconductor device, comprising:
- a packaging substrate having a first semiconductor device mounted in a first semiconductor device mounting region of the packaging substrate, and a second semiconductor device mounted in a second semiconductor device mounting region;
- a stress isolation structure (SIS) disposed on the packaging substrate proximate a perimeter of each of the first and the second semiconductor device mounting regions;
- and
- a cover over the SIS and the packaging substrate, the cover extending beyond a boundary of the SIS, a perimeter portion of the cover being attached to the packaging substrate, the perimeter portion of the cover enclosing the SIS, the cover having a first thickness over the first semiconductor device and a second thickness over the second semiconductor device, the second thickness being different from the first thickness, a composition of the cover being the same along a center axis of the cover, the center axis extending from a lowermost surface of the cover to an uppermost surface of the cover.
1 more element
A packaging device for a semiconductor device, comprising:
- a packaging substrate having a first semiconductor device and a second semiconductor device mounted in a first semiconductor device mounting region and a second semiconductor device mounting region of the packaging substrate, respectively;
- a stress isolation structure (SIS) disposed on the packaging substrate, a portion of the SIS being disposed proximate a perimeter of each of the first and the second semiconductor device mounting regions, the SIS comprising a first height proximate the first semiconductor device mounting region and a second height proximate the second semiconductor device mounting region, the first height being different from the second height;
- and
- a cover attached to a perimeter region of the packaging substrate, the cover having a uniform density, the cover and the packaging substrate forming an enclosed space, the SIS and the first and the second semiconductor devices being contained within the enclosed space.
1 more element
A semiconductor package, comprising:
- a packaging substrate having a semiconductor device mounting region and a conductive trace;
- a semiconductor device mounted in the semiconductor device mounting region;
- a stress isolation structure (SIS) disposed on the packaging substrate proximate at least a portion of a perimeter of the semiconductor device, a lower surface of the SIS being thermally and electrically coupled to the conductive trace;
- and
- a cover over the SIS and the semiconductor device, a perimeter of the cover being directly attached to the packaging substrate by an adhesive to form an enclosed space, the SIS and the semiconductor device being contained within the enclosed space.
2 more elements
Dependencies are inferred from the claim text.