Repair circuit and fuse circuit

A fuse circuit comprising:

• a first anti-fuse element;
• a first selection transistor connected between the first anti-fuse element and a first node;
• a first program transistor connected between the first node and a ground voltage;
• a first switch connected to the first node and configured to selectively output a first program output signal;
• a second anti-fuse element electrically disconnected from the first anti-fuse element;
• a second selection transistor connected between the second anti-fuse element and a second node;
• a second program transistor connected between the second node and the ground voltage;
• and
• a second switch connected to the second node and configured to selectively output a second program output signal.

A repair circuit of a semiconductor memory device, the repair circuit comprising:

• a first fuse circuit including a first fuse, and configured to output a first master signal indicating whether the first fuse has been programmed;
• a second fuse circuit including a plurality of second fuses,
• wherein each of the second fuses is configured to be programmed based on a result of comparing a number of bits of a defective input address having a first logic level with a number of bits of the defective input address having a second logic level opposite to the first logic level, and
• wherein the second fuse circuit is configured to generate a first address using the second fuses based on a program operation that depends on the result of comparing;
• a determination circuit configured to generate a detection signal based on the first master signal and the first address, the detection signal indicating whether a negative program operation has been performed on the second fuse circuit;
• and
• an output circuit configured to output either the first address or a second address that is an inverted address of the first address as a repair address in response to the detection signal, wherein a logic level of each of the bits of the repair address is the same as that of the defective input address.