Circuit and method for controlling internal test mode entry of an ASRAM chip
AssigneeIntegrated Silicon Solution (Shanghai), Inc.
InventorMingzhao Tong
Life of this patent
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Abstract
A circuit and method for controlling internal test mode entry of an Asynchronous Static Random Access Memory (ASRAM) chip wherein the circuit includes an address code comparator for detecting whether address codes inputted via an address bus of the ASRAM chip match a predefined validation code; a test mode detector for determining whether to let the ASRAM chip enter into an internal test mode; a test mode clock generator for generating a clock signal for the test mode decoder; and a test mode decoder for generating a test control signal. The circuit of the present application uses the existing pins of the ASRAM chip to input a special section of codes to trigger the ASRAM to enter into its internal test mode, thereby reducing the difficulty of testing the products.
Claims10
A method for controlling internal test mode entry of an Asynchronous Static Random Access Memory (ASRAM) chip, comprising:
- setting an enabling signal for an internal test mode active to start an internal test period, when two or more consecutive falling edges are detected in a second input signal at an output enable pin of the ASRAM chip and address codes inputted via an address bus coupled to the ASRAM chip are detected to match a validation code predefined in the ASRAM chip at each of the two or more consecutive falling edges, and when a first input signal at a write enable pin of the ASRAM chip is at a low level;
- and
- storing a test mode code inputted via the address bus and triggering the ASRAM chip into the internal test mode according to the test mode code at a following rising edge inputted at the output enable pin, when the first input signal at the write enable pin is at the low level.
A circuit for controlling internal test mode entry of an ASRAM chip, comprising:
- an address code comparator configured to detect whether address codes inputted via an address bus coupled to the ASRAM chip match a predefined validation code;
- a test mode detector configured to determine whether to let the ASRAM chip enter into an internal test mode according to a first input signal at a write enable pin of the ASRAM chip, a second input signal at an output enable pin of the ASRAM chip and an output signal of the address code comparator, wherein the ASRAM chip enters into the internal test mode when two or more consecutive falling edges are detected in the second input signal at the output enable pin, and the address codes inputted via the address bus are detected to match the predefined validation code at each of the two or more consecutive falling edges, and when the first input signal at the write enable pin is at a low level;
- a test mode clock generator configured to generate a clock signal according to an output signal of the test mode detector and the second input signal at the output enable pin;
- and
- a test mode decoder configured to generate a test control signal according to the output signal of the test mode detector, the clock signal outputted by the test mode clock generator and the address codes inputted via the address bus.
Dependencies are inferred from the claim text.