Fail address storage circuit, redundancy control circuit, method for storing fail address and method for controlling redundancy
AssigneeSK hynix Inc.
InventorYong-Ho Kong
Life of this patent
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Abstract
A redundancy control circuit includes: a fail address storage unit configured to store a fail address; a shared storage unit configured to store data as to whether a value stored in the fail address storage unit corresponds to both of a first address and a second address; an address comparator configured to compare a value stored in the fail address storage unit with a first input address and a second input address, respectively; and a redundancy controller configured to control a redundancy operation in response to a value stored in the shared storage unit and comparison results of the address comparator.
Claims8
A redundancy control circuit, comprising:
- a fail address storage unit;
- a shared storage unit configured to store data indicating whether a fail address is stored in the fail address storage unit and whether the fail address corresponds to both of row and column addresses;
- an address comparator configured to compare the fail address with a row input address, and compare a part of the fail address with a column input address;
- and
- a redundancy controller configured to control a row redundancy operation when the fail address is stored in the fail address storage unit, and control row and column redundancy operations when the fail address corresponds to both of the row and column addresses, based on the data stored in the shared storage unit and comparison results of the address comparator.
A redundancy control circuit, comprising:
- a fail address storage unit;
- a shared storage unit configured to store data indicating whether a fail address is stored in the fail address storage unit and whether the fail address corresponds to both of row and column addresses;
- an address comparator configured to compare a first group of bits and a second group of bits stored in the fail address storage unit with a row input address, and compare the second group of bits stored in the fail address storage unit with a column input address;
- and
- a redundancy controller configured to control a row redundancy operation when the fail address is stored in the fail address storage unit, and controls row and column redundancy operation when the fail address corresponds to both of the row and column addresses, based on the fail address stored in the shared storage unit and comparison results of the address comparator.
A method for controlling redundancy using a redundancy control circuit including the fail address storage circuit storing the fail address, comprising:
- activating a first enable signal and a second enable signal when a fail address stored in the fail address storing circuit corresponds to both of a row and column addresses at the time of a redundancy operation;
- and
- controlling a row redundancy operation by comparing the fail address with a row input address when the first enable signal is activated, and controlling the row redundancy operation by comparing the fail address with the row input address and a column redundancy operation by comparing a part of the fail address with a column input address when the second enable signal is activated.
Dependencies are inferred from the claim text.