System and method for testing address-swap faults in multiport memories
AssigneeFreescale Semiconductor, Inc.
InventorsRajesh Raina, Magdy S. Abadir
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Abstract
A system method of detecting address-swap faults in a multiport memory as described herein includes minimum testing for inversion faults and bit-swap faults for each port of the multiport memory. Different test types may be performed for inversion and bit-swap including pass/fail, and diagnostic testing for locating faulty ports. Pass/fail testing may be used for identifying whether the IC is good or bad, and additional diagnostic testing using additional cycles may be used for disabling faulty ports or correcting inverted address bits. The test method may be implemented as a function test or as a memory built-in self-test. The test method may be used during manufacturing test or during function design verification.
Claims20
A method of detecting address-swap faults in a multiport memory, comprising:
- initializing each addressable location with a first data value via a first port of the multiport memory;
- writing a second data value to a first address via the first port, wherein the second data value is different from the first data value;
- and
- for every port of the multiport memory other than the first port:
- reading a stored data value at the first address via the port, and
- failing the port when the stored data value is not equal to the second data value.
A method of detecting address-swap faults in a multiport memory, comprising:
- initializing each addressable location of the multiport memory with a first data value;
- and
- for each address according to at least one Walsh Hadamard Code:
- writing a second data value to the address via a first port of the multiport memory;
- and
- after said writing the second data value to the address via the first port, for every port other than the first port:
- reading a stored data value at the address via the port, and
- failing the port when the stored data value is not equal to the second data value.
A memory system, comprising:
- a memory including a multiport memory;
- and
- a memory test system that detects address-swap faults in said multiport memory, comprising:
- a pattern generator that generates test patterns;
- an address block that provides addresses to ports of said multiport memory;
- a read/write control block that controls read and write operations of each of said ports of said multiport memory;
- and
- a comparator that compares a data input with a data output for each of said ports of said multiport memory;
- and
- wherein said memory test system is operative to:
- initialize each addressable location of said multiport memory with a first data value via a first port;
- write a second data value to a first address via said first port, wherein said second data value is different from said first data value;
- for every port other than said first port of the multiport memory:
- read a stored data value at said first address via said port, and
- fail said port when said stored data value is not equal to said second data value.
Dependencies are inferred from the claim text.