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US 9,287,004 B2Granted
Semiconductor memory device and system having redundancy cells
AssigneeSamsung Electronics Co., Ltd.
InventorsSu-a Kim, Young-soo Sohn, Dae-hyun Kim
Life of this patent
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Abstract
In one embodiment, the memory device includes a memory cell array having at least a first memory cell group, a second memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, the second memory cell group includes a plurality of second memory cells associated with a second data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. A data line selection circuit is configured to provide a data path between an input/output node and one of the first data line, the second data and the redundancy data line.
Claims51
A memory device, comprising:
- a memory cell array having at least a first memory cell group, a second memory cell group, a first redundancy memory cell group and a second redundancy memory cell group, the first memory cell group including a plurality of first memory cells associated with a first data line, the second memory cell group including a plurality of second memory cells associated with a second data line, the first redundancy memory cell group including a plurality of redundancy memory cells associated with a first redundancy data line, and the second redundancy memory cell group including a plurality of redundancy memory cells associated with a second redundancy data line;
- and
- a data line selection circuit configured to provide a data path between an input/output node and one of the first data line, the second data, the first redundancy data line, and the second redundancy data line, wherein
- the data line selection circuit includes a first selection unit corresponding to a first memory cell group and a second selection unit corresponding to a second memory cell group,
- the first redundancy data line is connected to the first selection unit and the second redundancy data line is connected to the second selection unit,
- data from the first redundancy data line and the second redundancy data line are output through the first selection unit or the second selection unit according to a selected output data width, and
- one or more of the first data line and the second data line are simultaneously replaced with the one or more of the first redundancy data line and the second redundancy data line, respectively, based on the selected output data width.
4 more elements
A memory device, comprising:
- a memory cell array having at least first through nth memory cell groups and first and second redundancy memory cell groups, where n is greater than or equal to four, the first through nth memory cell groups associated with respective first through nth data lines, the first redundancy memory cell group associated with a first redundancy data line and the second redundancy memory cell group associated with a second redundancy data line;
- and
- a data line selection circuit configured to replace access to one of the first through nth memory cell groups via a respective one of the first through nth data lines with access to the first redundancy memory cell group via the first redundancy data line, and configured to simultaneously replace access to another of the first through nth memory cell groups via a respective one of the first through nth data lines with access to the second redundancy memory cell group via the second redundancy data line, wherein
- the first through nth memory cell groups are classified into a first region and a second region,
- when a first data width option is set, two data lines are simultaneously replaced with the first and second redundancy data lines, and
- when a second data width option is set, one data line among a plurality of data lines corresponding to the first region is replaced with the first redundancy data line, or one data line among a plurality of data lines corresponding to the second region is replaced with the second redundancy data line.
3 more elements
A memory device, comprising:
- a memory array having a plurality of memory cell groups and a redundancy memory cell group, each memory cell group associated with a respective data line, the redundancy memory cell group associated with a redundancy data line;
- a plurality of input/output nodes;
- and
- a data line selection circuit configured to provide data paths between (i) the plurality of input/output nodes and (ii) the data lines and the redundancy data line, the data line selection circuit including a selection unit associated with each of the plurality of input/output nodes, each selection unit associated with only two of the redundancy data line and the data lines, and
- the data line selection circuit configured to,
- provide data paths between odd ones of the plurality of input/output nodes and odd ones of the data lines in an odd mode of operation,
- provide data paths between even ones of the plurality of input/output nodes and even ones of the data lines in an even mode of operation, and
- replace access via one of the data lines with access via the redundancy data line such that a detected defective memory cell in one of the plurality of memory cell groups is replaced with one of the plurality of redundancy memory cells regardless of the even and odd operating mode, wherein
- the data line selection circuit includes,
- a first selection unit configured to transmit data in the even mode of operation,
- a second selection unit configured to transmit data in the odd mode of operation, and
- even/odd selection unit configured to provide data from the redundancy data line with the first selection unit in the even mode of operation and provide data from the redundancy data line with the second selection unit in the odd mode of operation.
9 more elements
A memory device, comprising:
- a first memory cell array including a first plurality of memory cell groups and a first redundancy memory cell group, each of the first plurality of memory cell groups associated with respective first data lines, the first redundancy memory cell group associated with one of the first data lines;
- a second memory cell array including a second plurality of memory cell groups and a second redundancy memory cell group, each of the second plurality of memory cell group associated with respective second data lines, and the second redundancy memory cell group associated with one of the second data lines;
- and
- a data line selection circuit configured to selectively provide data paths between the first data lines and a first set of a plurality of input/output nodes, and configured to selectively provide data paths between the second data lines and a second set of the plurality of input/output nodes, the data line selection circuit configured to selectively replace a detected defective memory cell in the first plurality of memory groups with a redundancy memory cell in the second redundancy memory cell group, wherein
- the data line selection circuit includes a plurality of first selection units corresponding to the first memory cell array and a plurality of second selection units corresponding to the second memory cell array,
- at least one redundancy data line corresponding to the first and second redundancy memory cell groups is shifted according to a data line shifting operation, and
- data from the second redundancy memory cell group is transmitted through one of the second data lines and one of the first selection units.
4 more elements
A method of replacing defective memory cells in a memory cell array having at least a first memory cell group, a second memory cell group, a first redundancy memory cell group and a second redundancy memory cell group, the first memory cell group including a plurality of first memory cells associated with a first data line, the second memory cell group including a plurality of second memory cells associated with a second data line, the first redundancy memory cell group including a plurality of redundancy memory cells associated with a first redundancy data line, and the second redundancy memory cell group including a plurality of redundancy memory cells associated with a second redundancy data line, the method comprising:
- providing, via a data line selection circuit, a data path between an input/output node and one of the first data line, the second data, the first redundancy data line and the second redundancy data line, wherein
- the data line selection circuit includes a first selection unit corresponding to a first memory cell group and a second selection unit corresponding to a second memory cell group,
- the first redundancy data line is connected to the first selection unit and the second redundancy data line is connected to the second selection unit,
- data from the first redundancy data line and the second redundancy data line are output through the first selection unit or the second selection unit according to a selected output data width, and
- one or more of the first data line and the second data line are simultaneously replaced with the one or more of the first redundancy data line and the second redundancy data line, respectively, based on the selected output data width.
2 more elements
A method of replacing defective memory cells in a memory cell array having at least first through nth memory cell groups and first and second redundancy memory cell groups, where n is greater than or equal to four, the first through nth memory cell groups associated with respective first through nth data lines, the first redundancy memory cell group associated with a first redundancy data line and the second redundancy memory cell group associated with a second redundancy data line, the method comprising:
- replacing access to one of the first through nth memory cell groups via a respective one of the first through nth data lines with access to the first redundancy memory cell group via the first redundancy data line;
- and
- simultaneously replacing access to another of the first through nth memory cell groups via a respective one of the first through nth data lines with access to the second redundancy memory cell group via the second redundancy data line, wherein
- the first through nth memory cell groups are classified into a first region and a second region,
- when a first data width option is set, two data lines are simultaneously replaced with the first and second redundancy data lines, and
- when a second data width option is set, one data line among a plurality of data lines corresponding to the first region is replaced with the first redundancy data line, or one data line among a plurality of data lines corresponding to the second region is replaced with the second redundancy data line.
3 more elements
A method of replacing defective memory cells in a memory array having a plurality of memory cell groups and a redundancy memory cell group, each memory cell group associated with a respective data line, the redundancy memory cell group associated with a redundancy data line, the method comprising:
- providing data paths between (i) a plurality of input/output nodes and (ii) the data lines and the redundancy data line using a plurality of selection units included in a data line selection circuit, each selection unit associated with one of the plurality of input/output nodes, each selection unit associated with only two of the redundancy data line and the data lines, the providing including,
- providing data paths between odd ones of the plurality of input/output nodes and odd ones of the data lines in an odd mode of operation,
- providing data paths between even ones of the plurality of input/output nodes and even ones of the data lines in an even mode of operation, and
- replacing access via one of the data lines with access via the redundancy data line such that a detected defective memory cell in one of the plurality of memory cell groups is replaced with one of the plurality of redundancy memory cells regardless of the even and odd operating mode, wherein
- the data line selection circuit includes,
- a first selection unit configured to transmit data in the even mode of operation,
- a second selection unit configured to transmit data in the odd mode of operation, and
- even/odd selection unit configured to provide data from the redundancy data line with the first selection unit in the even mode of operation and provide data from the redundancy data line with the second selection unit in the odd mode of operation.
5 more elements
A method of replacing defective memory cells in a memory device include a first memory cell array and a second memory cell array,
- the first memory cell array including a first plurality of memory cell groups and a first redundancy memory cell group, each of the first plurality of memory cell groups associated with respective first data lines, the first redundancy memory cell group associated with one of the first data lines,
- the second memory cell array including a second plurality of memory cell groups and a second redundancy memory cell group, each of the second plurality of memory cell groups associated with respective second data lines, and the second redundancy memory cell group associated with one of the second data lines,
- the method comprising:
- selectively replacing, via a data line selection circuit, a detected defective memory cell in the first plurality of memory groups with a redundancy memory cell in the second redundancy memory cell group, wherein
- the data line selection circuit includes a plurality of first selection units corresponding to the first memory cell array and a plurality of second selection units corresponding to the second memory cell array,
- at least one redundancy data line corresponding to the first and second redundancy memory cell groups is shifted according to a data line shifting operation, and
- data from the second redundancy memory cell group is transmitted through one of the second data lines and one of the first selection units.
4 more elements
Dependencies are inferred from the claim text.