US 9,287,003 B2 · Multi-cycle write leveling

Abstract

A memory controller includes logic to determine corresponding reference voltage values and delay values for one or more memory devices. The memory controller includes a command-address (CA) interface to send a command to a memory device to set a reference voltage value of the memory device to a test value, a data interface to write a data pattern to the memory device and read the data pattern from the memory device, and test reference voltage logic to perform a density check on at least a portion of the data pattern read from the memory device and determine whether the test value is a potential reference voltage value based on the density check. An operational reference voltage value selected from one or more potential reference voltage values may be used to determine a delay value.

Claims20

Dependent claims

A method comprising:

sending, by a memory controller, a command to a memory device, the command to cause the memory device to set a reference voltage value of the memory device to a test value;
writing, by the memory controller, a first data pattern to the memory device;
reading, by the memory controller, the first data pattern from the memory device;
performing, by the memory controller, a density check on at least a portion of the first data pattern read from the memory device;
and
determining, by the memory controller, that the test value comprises a potential reference voltage value for the memory device when the at least the portion of the first data pattern passes the density check.

3 more elements

Dependencies are inferred from the claim text.

Multi-cycle write leveling

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Multi-cycle write leveling

Life of this patent

Abstract

Claims20