Semiconductor devices
AssigneeSK hynix Inc.
InventorsJoon Woo Choi, Chang Ki Baek
Life of this patent
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Abstract
A semiconductor device includes a first input/output (I/O) part buffering command/address (C/A) signals inputted through a first pad part to generate delay address signals, an internal address generator generating a plurality of internal address signals according to a level combination of the delay address signals, and a second I/O part including a plurality of fuses selected by the plurality of internal address signals in a test mode. The plurality of fuses of the second I/O part are programmed according to logic levels of data inputted to the second I/O part through a second pad part to control I/O characteristics of the second I/O part.
Claims25
A semiconductor device comprising:
- a first input/output (I/O) part suitable for buffering command/address (C/A) signals inputted through a first pad part to generate delay address signals;
- an internal address generator suitable for generating a plurality of internal address signals according to a level combination of the delay address signals;
- and
- a second I/O part including a plurality of fuses selected by the plurality of internal address signals in a test mode,
- wherein the plurality of fuses of the second I/O part are programmed according to logic levels of data inputted to the second I/O part through a second pad part to control I/O characteristics of the second I/O part.
A semiconductor device comprising:
- a first input/output (I/O) part including first to fourth fuses selected by first and second command/address (C/A) signals inputted through a first pad part during a first period in a test mode, the first to fourth fuses being programmed according to logic levels of the first and second C/A signals to control a first I/O characteristic of the first I/O part during a second period in the test mode;
- and
- a second I/O part including fifth to eighth fuses selected according to logic levels of first and second data inputted through a second pad part during a third period in the test mode, the fifth to eighth fuses being programmed according to logic levels of the first and second data to control a second I/O characteristic of the second I/O part during a fourth period in the test mode.
A semiconductor device comprising:
- first to fourth command/address (C/A) input/output (I/O) units configured to buffer a plurality of C/A signals to generate a plurality of delay address signals;
- an internal address generator configured to generate a plurality of internal address signals sequentially enabled according to a level combination of the plurality of delay address signals;
- and
- first to fourth data I/O units including a plurality of fuses sequentially selected by the plurality of internal address signals in a test mode,
- wherein the plurality of fuses are programmed according to logic levels of data.
Dependencies are inferred from the claim text.