Read only memory having multi-bit line bit cell

A memory device, comprising:

• a plurality of memory cells including a corresponding plurality of transistors, wherein a first memory cell includes a first transistor for storing first, second, third, and fourth data values;
• a plurality of word lines including a first word line for activating the first transistor;
• a plurality of pairs of bit lines including first and second pairs of bit lines that correspond to the first transistor, wherein the first and second pairs of bit lines include first and second bit lines, and third and fourth bit lines, respectively, and wherein the first, second, third, and fourth bit lines are for retrieving the first, second, third, and fourth data values, respectively;
• and
• a plurality of source lines including first and second source lines that correspond to the first transistor, wherein the first and second source lines are for retrieving the first and second data values, and the third and fourth data values, respectively, and
• wherein the first transistor has a gate terminal connected to the first word line for receiving a word line enable signal, a first diffusion terminal connected to ground, and a second diffusion terminal connected to at least one of the first source line, the second source line, the first bit line, the second bit line, the third bit line, and the fourth bit line, for determining the first, second, third, and fourth data values,
• wherein the first and second data values correspond to a first logic value when the second diffusion terminal is connected to the first source line, the first logic value and a second logic value, respectively, when the second diffusion terminal is connected to the first bit line, the second and first logic values, respectively, when the second diffusion terminal is connected to the second bit line, and the second logic value when the second diffusion terminal is floating.

A memory device layout, comprising:

• a plurality of active regions formed in a semiconductor substrate, wherein a first active region includes first and second diffusion regions;
• a plurality of gate electrode strips including a first gate electrode strip formed over the first active region, wherein the first gate electrode strip, and the first and second diffusion regions form a first transistor, and wherein the first transistor stores first and second data values;
• a first metal strip connected to the first gate electrode strip, wherein the first gate electrode strip receives a first voltage signal by way of the first metal strip for reading the first and second data values;
• a second metal strip connected to ground and the first diffusion region, wherein the first diffusion region is connected to ground by way of the second metal strip;
• a third metal strip connected to the second diffusion region;
• and
• fourth, fifth, and sixth metal strips, wherein the second diffusion region is connected to at least one of the fourth, fifth, and sixth metal strips by way of the third metal strip for receiving a second voltage signal, for determining the first and second data values.