Read only memory array architecture and methods of operation
AssigneeBroadcom Corporation
InventorsNarayana Rao Vedula, Dechang Sun, Myron Buer
Life of this patent
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Abstract
An encoded ROM array structure couples a first one of a first set of bitlines to a second one of a second set of bitlines through a transistor when the wordline connected to the gate terminal of that transistor is asserted. This encoded arrangement can be extended to any number of encoded bitlines, e.g., 2, 4, 8, 16, and so on. Each of the first plurality and second sets of bit lines are coupled to circuits for charging and discharging the bitlines. To read data from the first set of bit lines, the second set of bitlines is discharged, and vice versa.
Claims20
A read only memory (ROM) array, comprising:
- a first field effect transistor (FET) in a first column of FETs, the first FET having a first source/drain (S/D) terminal coupled to a first S/D node, a second S/D terminal coupled to a second S/D node, and a gate terminal coupled to a signal source;
- a second FET in a second column of FETs, the second FET having a third S/D terminal coupled to a third S/D node and a fourth S/D terminal coupled to a fourth S/D node;
- a first plurality of bit lines, each one of which is coupleable to the first S/D node;
- a second plurality of bit lines, each one of which is coupleable to the second S/D node or the third S/D node;
- and
- a third plurality of bit lines, each one of which is coupleable to the fourth S/D node.
A read only memory (ROM) encoded with a dual-side programming arrangement, comprising:
- a plurality of switchable conductive pathways disposed in an array of rows and columns, each switchable conductive pathway having a control terminal, a first terminal and a second terminal;
- a first set of bit lines disposed adjacent a first side of a first column of switchable conductive pathways;
- a second set of bit lines disposed adjacent a second side of the first column of switchable conductive pathways, and adjacent a first side of a second column of switchable conductive pathways;
- a third set of bit lines disposed adjacent a second side of the second column of switchable conductive pathways;
- a first word line coupled to the control terminal of each switchable conductive pathway in a first row of switchable conductive pathways;
- first circuitry coupled to the first set of bit lines and configured to discharge the first set of bit lines when the second set of bit lines are to be read;
- and
- second circuitry coupled the second set of bit lines and configured to discharge the second set of bit lines when the first set of bit lines are to be read;
- wherein each one of the first set of bit lines is coupleable to a first terminal of a first switchable conductive pathway disposed in the first row and in the first column, each one of the second set of bit lines is coupleable to the second terminal of the first switchable conductive pathway or is coupled to a first terminal of a second switchable conductive pathway disposed in the first row and in the second column;
- a first one of the first set of bit lines is coupled to the first terminal of the first switchable conductive pathway, a first one of the second set of bit lines is coupled to the second terminal of the first switchable conductive pathway, and a second one of the second set of bit lines is coupled to the first terminal of the second switchable conductive pathway.
A read only memory (ROM) array, comprising:
- a first field effect transistor (FET) in a first column of FETs, the first FET having a first source/drain (S/D) terminal coupled to a first S/D node, a second S/D terminal coupled to a second S/D node, and a gate terminal coupled to a signal source;
- a second FET in a second column of FETs, the second FET having a third S/D terminal coupled to a third S/D node and a fourth S/D terminal coupled to a fourth S/D node;
- a first plurality of bit lines, each one of which is coupleable to the first S/D node;
- a second plurality of bit lines, each one of which is coupleable to the second S/D node and the third S/D node;
- and
- a third plurality of bit lines, each one of which is coupleable to the fourth S/D node.
Dependencies are inferred from the claim text.