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US 9,286,995 B2Granted
Memory system and control method
AssigneeKabushiki Kaisha Toshiba
InventorsJiezhi Chen, Yuichiro Mitani
Life of this patent
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Abstract
A memory system according to embodiments comprises a memory chip that includes a memory cell array having a plurality of memory cells, a first writing unit that writes first data in a first memory cell in the memory cell array, and a second writing unit that writes second data in a second memory cell which is adjacent to the first memory cell. The second data is used in adjusting a threshold value of the first memory cell.
Claims8
A memory system comprising:
- a memory chip that includes a memory cell array having a plurality of memory cells;
- a first writing unit that writes first data in a first memory cell in the memory cell array;
- and
- a second writing unit that writes second data, which is used in adjusting a threshold value of the first memory cell, in a second memory cell which is adjacent to the first memory cell.
1 more element
A control method for a memory system that includes a memory chip including a memory cell array having a plurality of memory cells, the control method comprising:
- writing first data in a first memory cell in the memory cell array;
- and
- writing second data, which is used in adjusting a threshold value of the first memory cell, in a second memory cell which is adjacent to the first memory cell.
Dependencies are inferred from the claim text.