Method of reducing hot electron injection type of read disturb in dummy memory cells

A non-volatile memory device, comprising:

• a selected NAND string comprising a drain-side select gate transistor at a drain-side of the selected NAND string, a first dummy memory cell adjacent to the drain-side select gate transistor of the selected NAND string, a selected memory cell and unselected memory cells;
• an unselected NAND string comprising a drain-side select gate transistor at a drain-side of the unselected NAND string, a first dummy memory cell adjacent to the drain-side select gate transistor of the unselected NAND string, an unselected memory cell corresponding to the selected memory cell and other unselected memory cells;
• a select gate line connected to the drain-side select gate transistor of the selected NAND string and the drain-side select gate transistor of the unselected NAND string;
• a first dummy word line connected to the first dummy memory cell of the selected NAND string and the first dummy memory cell of the unselected NAND string;
• a selected word line connected to the selected memory cell and the corresponding unselected memory cell;
• unselected word lines connected to the unselected memory cells of the selected NAND string and the other unselected memory cells of the unselected NAND string;
• a bit line connected to the selected NAND string and to the unselected NAND string;
• and
• a control circuit, the control circuit is configured to:
• provide one increase of a voltage on the select gate line, one increase of a voltage on the first dummy word line and one increase of voltages of the unselected word lines while the bit line is at a driven voltage;
• subsequently provide a decrease of the voltage on the select gate line;
• subsequently provide another increase of the voltage on the first dummy word line and another increase of the voltages of the unselected word lines;
• and
• subsequently sense the selected memory cell while one or more voltages are provided on the selected word line.

A memory controller, comprising:

• a storage device comprising a set of instructions;
• and
• a processor operable to execute the set of instructions, the set of instructions comprising:
• instructions to connect a channel of an unselected NAND string to a bit line while the bit line is at a driven voltage, wherein the bit line is connected to a selected NAND string, a select gate line is connected to a drain-side select gate transistor at a drain-side of the unselected NAND string and a drain-side select gate transistor at a drain-side of the selected NAND string, a first dummy word line is connected to a first dummy memory cell in the unselected NAND string adjacent to the drain-side select gate transistor of the unselected NAND string and to a first dummy memory cell in the selected NAND string adjacent to the drain-side select gate transistor of the selected NAND string, a selected word line is connected to a selected memory cell in the selected NAND string and to a corresponding unselected memory cell in the unselected NAND string, unselected word lines are connected to unselected memory cells in the selected NAND string and to corresponding unselected memory cells in the unselected NAND string, and the instructions to connect comprise instructions to step up a voltage on the select gate line, step up a voltage on the first dummy word line, and step up a voltage on the unselected word lines;
• instructions to, after the connecting, disconnect the channel of the unselected NAND string from the bit line, the instructions to disconnect comprising instructions to step down the voltage on the select gate line;
• and
• instructions to, while the channel of the unselected NAND string is disconnected from the bit line, further step up the voltage of the first dummy word line, and subsequently sense the selected memory cell while one or more voltages are provided on the selected word line.