Flash memory system with EEPROM functionality

A non-volatile memory device comprising:

• an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line;
• and
• a first source line select line for controlling access by a first source line to the byte of memory cells;
• wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.

A non-volatile memory device comprising:

• an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line;
• and
• a word line select transistor for controlling access by a word line to the byte of memory cells;
• wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.

A non-volatile memory device comprising:

• an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line;
• and
• a first source line select transistor for controlling access by a first source line to the byte of memory cells;
• wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.

A non-volatile memory device comprising:

• an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line;
• wherein each column of memory cells is coupled to two bit lines;
• and
• wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.

A non-volatile memory device comprising:

• an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line;
• and
• a source line select read line coupled to a pair of bytes of memory cells that enable the reading of both bytes at the same time;
• wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.

A non-volatile memory device comprising:

• an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line;
• and
• a word line for accessing two rows of memory cells;
• wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.

A non-volatile memory device comprising:

• an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line;
• wherein half of the rows of memory cells are not used during operation of the device;
• and
• wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.

A non-volatile memory device comprising:

• an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a control gate for connecting to a control gate line, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line;
• and
• a source line select read line coupled to a pair of bytes of memory cells that enable the reading of both bytes at the same times;
• wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.

A non-volatile memory device comprising:

• an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a control gate for connecting to a control gate line, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line;
• and
• a control gate select line for controlling access by a word line to the control gate of each memory cell in the byte of memory cells;
• wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.

A non-volatile memory device comprising:

• an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a control gate for connecting to a control gate line, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line;
• wherein a bitline is used to pull down the source line to a low voltage for the selected bitline during a read operation;
• and
• wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.

A non-volatile memory device comprising:

• an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a control gate for connecting to a control gate line, an erase gate for connecting to an erase gate line, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line;
• wherein a bitline is used to pull down the source line to a low voltage for the selected bitline during a read operation;
• and
• wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.

A non-volatile memory device comprising:

• an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a control gate for connecting to a control gate line, an erase gate for connecting to an erase gate line, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line;
• and
• a source line select read line coupled to a pair of bytes of memory cells that enable the reading of both bytes at the same time;
• wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.

A non-volatile memory device comprising:

• an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a control gate for connecting to a control gate line, an erase gate for connecting to an erase gate line, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line;
• and
• a control gate select line for controlling access by a word line to the control gate of each memory cell in the byte of memory cells;
• wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.