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US 9,286,979 B2Granted
Method and structure for resistive switching random access memory with high reliable and high density
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChun-Yang Tsai, Yu-Wei Ting, Kuo-Ching Huang
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Abstract
The present disclosure provides a resistive random access memory (RRAM) structure. The RRAM structure includes a bottom electrode on a substrate; a resistive material layer on the bottom electrode, the resistive material layer having filament features with a filament ratio greater than about 0.5; and a top electrode on the resistive material layer.
Claims20
An apparatus comprising:
- a memory device that includes a resistive material layer having filament features with a filament ratio that is equal to or greater than about 0.5, wherein the filament features has a size distribution with a characteristic size Sm, wherein the filament features includes a first subset features each with a radius less than Sm and a second subset features each with a radius greater than Sm, and wherein the filament ratio is defined as As/(As+Al), wherein As is a first sum of sectional areas of the first subset features and Al is a second sum of sectional areas of the second subset features.
An apparatus comprising:
- an interconnect structure that includes:
- a first metal layer having a first metal feature;
- a second metal layer having a second metal feature that is disposed over the first metal layer;
- a first via feature overlying the first metal feature and electrically coupled with the first metal feature;
- and
- a second via feature underlying the second metal feature and electrically coupled with the second metal feature;
- and
- a memory device that includes a resistive material layer having filament features with a filament ratio that is equal to or greater than about 0.5, wherein the memory device is overlying and electrically coupled with the first via feature and wherein the memory device is underlying and electrically coupled with the second via feature.
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A method comprising:
- performing a first forming operation on a memory device by applying a first voltage having a first polarity;
- performing a second forming operation on the memory device by applying a second voltage having a second polarity that is opposite to the first polarity;
- setting the memory device by applying a third voltage having the first polarity to the memory device, wherein the third voltage is different than the first voltage and different than the second voltage;
- and
- resetting the memory device by applying a fourth voltage having the second polarity to the memory device, wherein the fourth voltage is different than the first voltage and different than the second voltage, and
- wherein the memory device include a resistive material layer,
- wherein after performing the first and second forming operations the resistive material layer has filament features with a filament ratio that is equal to or greater than about 0.5, and
- wherein the filament features has a size distribution with a characteristic size Sm, wherein the filament features includes a first subset features each with a radius less than Sm and as subset features each with a radius greater than Sm, and wherein the filament ratio is defined as As/(As+Al), wherein As is a first sum of sectional areas of the first subset features and Al is a second sum of sectional areas of the second subset features.
5 more elements
Dependencies are inferred from the claim text.