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US 9,286,975 B2Granted
Mitigating read disturb in a cross-point memory
AssigneeIntel Corporation
InventorsDaniel J. Chu, Kiran Pangal, Nathan R. Franklin, Prashant S. Damle, Hu Chaohong
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Abstract
The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.
Claims12
An apparatus comprising:
- a memory controller configured to select a target memory cell for a memory access operation, the memory controller comprising:
- a sense module configured to determine whether a snap back event occurs during a sensing interval of a read completion time interval;
- and
- a write back module configured to write back, during said read completion time interval, a logic one to the memory cell in response to a snap back event being detected during said read completion time interval;
- and
- switch circuitry comprising a word line (WL) switch configured to couple a target WL to a WL select voltage source, and a bit line (BL) switch configured to couple a target BL to a BL select voltage source;
- wherein the memory controller is configured to control the switch circuitry to turn at least one of the WL switch or the BL switch partially OFF at or near the start of the sensing interval and to turn said at least one of the WL switch or the BL switch ON in response to a snap back event being detected during said read completion time interval.
4 more elements
A method comprising:
- selecting, by a memory controller, a target memory cell for a memory access operation;
- determining, by a sense module, whether a snap back event occurs during a sensing interval of a read completion time interval;
- writing back, by a write back module during said read completion time interval, a logic one to the memory cell in response to a snap back event being detected during said read completion time interval;
- controlling, by the memory controller, switch circuitry to turn at least one of a WL switch or a BL switch partially OFF at or near the start of the sensing interval;
- and
- controlling, by the memory controller, the switch circuitry to turn said at least one of the WL switch or the BL switch ON in response to a snap back event being detected during said read completion time interval.
3 more elements
A system comprising:
- a processor;
- a cross-point memory array comprising a target memory cell, a target word line (WL) and a target bit line (BL), the target memory cell coupled between the target WL and the target BL;
- a memory controller coupled to the processor and the cross-point memory array, the memory controller configured to select a target memory cell for a memory access operation, the memory controller comprising:
- a sense module configured to determine whether a snap back event occurs during a sensing interval of a read completion time interval;
- and
- a write back module configured to write back, during said read completion time interval, a logic one to the memory cell in response to a snap back event being during said read completion time interval;
- and
- switch circuitry comprising a word line (WL) switch configured to couple a target WL to a WL select voltage source, and a bit line (BL) switch configured to couple a target BL to a BL select voltage source;
- wherein the memory controller is configured to control the switch circuitry to turn at least one of the WL switch or the BL switch partially OFF at or near the start of the sensing interval and to turn said at least one of the WL switch or the BL switch ON in response to a snap back event being detected during said read completion time interval.
6 more elements
Dependencies are inferred from the claim text.