Method, memory controller and system for reading data stored in flash memory

A memory controller for reading data stored in a flash memory, the memory controller comprises:

• a control logic for controlling the flash memory to perform a read operation upon a first page of the flash memory and for obtaining a first codeword of the first page;
• a log-likelihood ratio (LLR) mapping unit, for obtaining a first set of LLR mapping values of the first codeword according to a first LLR mapping rule;
• a decoding circuit, for performing an error correction operation according to the first set of LLR mapping values;
• and
• a LLR training unit, for gathering a statistics feature of a second codeword of the flash memory and correct data of the flash memory, and a statistics feature of a part of the first codeword and correct data of the part of the first codeword to obtain a second LLR mapping rule,
• wherein the LLR mapping unit is further for obtaining a second set of LLR values of the first codeword according to the second LLR mapping rule, if the error correction operation performed according to the first set of LLR mapping values indicates that a first sector of the first page is uncorrectable and the second sector neighboring to the first sector is correctable, the LLR training unit is further for gathering a statistics feature of a second codeword of the second sector and correct data of the second sector to obtain the second LLR mapping rule, and the decoding circuit is further for performing the error correction operation according to the set of second LLR mapping values.

A memory system for reading data stored in a flash memory, the memory system comprises:

• a control logic for controlling the flash memory to perform a read operation upon a first page of the flash memory and for obtaining a first codeword of the first page;
• a log-likelihood ratio (LLR) mapping unit, for obtaining a first set of LLR mapping values of the first codeword according to a first LLR mapping rule;
• a decoding circuit, for performing an error correction operation according to the first set of LLR mapping values;
• a LLR training unit, for gathering a statistics feature of a second codeword of the flash memory and correct data of the flash memory, and a statistics feature of a part of the first codeword and correct data of the part of the first codeword to obtain a second LLR mapping rule,
• wherein the LLR mapping unit is further for obtaining a second set of LLR values of the first codeword according to the second LLR mapping rule, if the error correction operation performed according to the first set of LLR mapping values indicates that a first sector of the first page is uncorrectable and a second sector neighboring to the first sector is correctable, the LLR training unit is further for gathering a statistics feature of the second codeword of the second sector and correct data of the second sector to obtain the second LLR mapping rule, and the decoding circuit is further for performing the error correction operation according to the second set of LLR mapping values.