US 9,286,971 B1 · Method and circuits for low latency initialization of static random access memory

Abstract

A method and various circuit embodiments for low latency initialization of an SRAM are disclosed. In one embodiment, an IC includes an SRAM coupled to at least one functional circuit block. The SRAM includes a number of storage location arranged in rows and columns. The functional circuit block and the SRAM may be in different power domains. Upon initially powering up or a restoration of power, the functional circuit block may assert an initialization signal to begin an initialization process. Responsive to the initialization signal, level shifters may force assertion of various select/enable signals in a decoder associated with the SRAM. Thereafter, initialization data may be written to the SRAM. Writing initialization data may be performed on a row-by-row basis, with all columns in a row being written to substantially simultaneously.

Claims20

Dependent claims

An integrated circuit comprising:

a functional circuit block;
a static random access memory (SRAM) coupled to the functional circuit block, wherein the SRAM includes a plurality of storage locations organized into a plurality of rows and a plurality of columns;
and
a plurality of level shifter circuits including:
a first level shifter configured to disable a precharge signal received by the SRAM responsive to assertion of an initialization signal by the functional circuit block;
and
a second level shifter configured to force assertion of a write enable signal received by the SRAM responsive to assertion of the initialization signal;
wherein the SRAM includes a decoder configured to force assertion of each of a plurality of column select signals received by the SRAM responsive to assertion of the initialization signal.

5 more elements

An integrated circuit comprising:

a static random access memory (SRAM) having a plurality of rows and a plurality of banks, wherein each of the plurality of rows extends across the plurality of banks;
a decoder circuit configured to, responsive to receiving an initialization signal from a functional circuit block of the integrated circuit, cause assertion of each of a plurality of bank select signals associated with respective ones of the plurality of banks and further cause assertion of a write enable signal;
wherein the functional circuit block is configured to perform an initialization of the SRAM by holding the initialization signal asserted and concurrently writing initialization data into a given row across each of the plurality of banks of the SRAM and further configured to repeat concurrently writing initialization data into each additional row across each of the plurality of banks of the SRAM until initialization data has been written into each of the plurality of rows.

Dependencies are inferred from the claim text.

Method and circuits for low latency initialization of static random access memory

Life of this patent

Method and circuits for low latency initialization of static random access memory

Life of this patent

Abstract

Claims20