Memory circuit for pre-charging and write driving
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMing-Zhang Kuo, Cheng-Chung Lin, Ho-Chieh Hsieh, Kuo Feng Tseng, Sang Hoo Dhong
Life of this patent
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Abstract
A memory includes a word line, a bit line and a complementary bit line. A memory cell has a data node coupled to the bit line and a complementary data node coupled to the complementary bit line. The word line controls access to the memory cell. A circuit is coupled to the bit line and the complementary bit line. The circuit is configured to pull up to a high voltage, pull down to a low voltage, or float the bit line and the complementary bit line based on a first timing of pre-charging and a second timing of write driving. The first timing and the second timing are synchronized.
Claims17
A memory, comprising:
- a word line;
- a bit line and a complementary bit line;
- a memory cell having a data node coupled to the bit line and a complementary data node coupled to the complementary bit line, wherein the word line controls access to the memory cell;
- and
- a circuit coupled to the bit line and the complementary bit line, wherein the circuit is configured to pull up to a high voltage, pull down to a low voltage, or float the bit line and the complementary bit line based on a first timing of pre-charging and a second timing of write driving, wherein the first timing and the second timing are synchronized by control signals and further wherein the circuit comprises a first PMOS transistor coupled between a high voltage node and the bit line, a second PMOS transistor coupled between the high voltage node and the complementary bit line, a first NMOS transistor coupled between a low voltage node and the bit line, a second NMOS transistor coupled between the low voltage node and the complementary bit line, and wherein the circuit is configured to turn on the first PMOS transistor and the second PMOS transistor for pre-charging.
A method, comprising:
- coupling a circuit to a bit line and a complementary bit line of a memory cell;
- and
- the circuit pulling up to a high voltage, pulling down to a low voltage, or floating the bit line and the complementary bit line based on a first timing of pre-charging and a second timing of write driving, wherein the first timing and the second timing are synchronized, and further the circuit turns turning on a first PMOS transistor of the circuit and a second PMOS transistor of the circuit for pre-charging, wherein the first PMOS transistor is coupled between a high voltage node and the bit line, and the second PMOS transistor is coupled between the high voltage node and the complementary bit line.
A memory, comprising:
- a word line;
- a bit line and a complementary bit line;
- a memory cell comprising cross-coupled inverters and having a data node coupled to the bit line and a complementary data node coupled to the complementary bit line, wherein the word line controls access to the memory cell;
- and
- a circuit comprising a first PMOS transistor coupled between a high voltage node and the bit line, a second PMOS transistor coupled between the high voltage node and the complementary bit line, a first NMOS transistor coupled between a low voltage node and the bit line, and a second NMOS transistor coupled between the low voltage node and the complementary bit line, wherein the circuit is configured to pull up to a high voltage, pull down to a low voltage, or float the bit line and the complementary bit line based on a first timing of pre-charging and a second timing of write driving, and ending of the first timing of pre-charging and starting of the second timing of write driving is performed simultaneously, and wherein the circuit is configured to turn on the first PMOS transistor and the second PMOS transistor for pre-charging.
Dependencies are inferred from the claim text.