Method for clock control in dynamic random access memory devices
AssigneeNanya Technology Corporation
InventorsDebra Bell, Kallol Mazumder
Life of this patent
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Abstract
A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. Control logic extends and reduces the multiple-cycle command signal to provide additional functions such as burst length and burst chop. Additional control logic is configured to determine whether a clock signal is enabled in output control logic circuitry according to the multiple-cycle command and logic level generated in the output logic circuitry.
Claims4
A method for clock control in dynamic random access memory devices, comprising the steps of:
- transitioning a logic level according to availability of an active zone of a dQ-Enable-Delay (QED) shifter stack, or whether a gap command signal is received;
- calculating the logic level with a logic level of a clock signal for generating a result;
- wherein the calculated logic level is configured to enable the clock signal according to the result, wherein the result is a first result;
- and
- wherein the calculated logic level is configured to disable the clock signal according to the result, wherein the result is a second result.
Dependencies are inferred from the claim text.