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US 9,286,965 B2Granted
Memory refresh method and devices
AssigneeRambus Inc.
InventorsRichard Perego, Thomas Vogelsang, John Brooks
Life of this patent
Estimating the term…
Abstract
The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.
Claims17
An integrated circuit device that controls a memory device, the integrated circuit device comprising:
- a circuit configured to:
- receive an activate command and a data access command;
- and
- responsive to receiving the activate command and the data access command, provide:
- a bank address, wherein the bank address identifies a bank of a plurality of banks in a memory device;
- a first row address that identifies a first row within the bank of the memory device for a memory access;
- and
- a second row address that identifies a second row within the bank of the memory device to perform a refresh operation;
- and
- a command interface coupled to the circuit, the command interface configured to output the bank address, the first row address, and the second row address provided by the circuit to the memory device, wherein the first row address and the second row address are simultaneously output to the memory device.
7 more elements
A memory module comprising:
- a memory device including a plurality of banks, each bank of the plurality of banks having a plurality of storage cells;
- a circuit configured to:
- receive an activate command and a data access command;
- and
- responsive to receiving the activate command and the data access command, provide:
- a bank address, wherein the bank address identifies a bank of the plurality of banks;
- a first row address that identifies a first row of memory cells within the bank for a memory access;
- and
- a second row address that identifies a second row of memory cells within the bank to perform a refresh operation;
- a command interface coupled to the circuit, the command interface configured to output the bank address, the first row address, and the second row address provided by the circuit;
- a data interface coupled between the plurality of the banks and the command interface, the data interface configured to receive the bank address, the first row address, and the second row address from the command interface;
- a first plurality of sense amplifiers to sense, in response to the bank address and the first row address, the first row of memory cells in the bank;
- and
- a second plurality of sense amplifiers to refresh the second row of memory cells in the bank based on the second row address, wherein the second plurality of sense amplifiers refreshes the second row of memory cells concurrently with the first plurality of sense amplifiers sensing the first row of memory cells.
11 more elements
A method of operation in a memory module comprising a memory device including a plurality of banks, the method comprising:
- receiving an activate command and a data access command;
- responsive to receiving the activate command and the data access command, determining a bank address that identifies a bank of the plurality of banks, a first row address that identifies a first row of memory cells within the bank for a memory access, and a second row address that identifies a second row of memory cells within the bank to perform a refresh operation;
- sensing, by a first plurality of sense amplifiers included in the memory module, a first row of memory cells in the bank based on the bank address and the first row address;
- and
- refreshing, by a second plurality of sense amplifiers included in the memory module, a second row of memory cells in the bank concurrently with the first row of memory cells being sensed by the first plurality of sense amplifiers, the second row of memory cells refreshed based on the bank address and the second row address.
2 more elements
Dependencies are inferred from the claim text.