US 9,286,961 B1 · Memory controller half-clock delay adjustment

Abstract

A method and apparatus for reducing a number of delay elements used in providing a delayed data strobe signal is disclosed. The method includes determining a number of delay elements of a master delay locked loop (DLL) needed to provide a calibrated delay of a clock signal (i.e. the data strobe). The method also include determining an integer number of half clock periods within the calibrated delay, and determining a second number of delay elements within the calibrated delay. If the integer number of half clock periods within the calibrated delay is zero, a slave DLL may be programmed with the first number of delay elements. However, if the number of half clock periods is non-zero, then a third number of delay elements is calculated by subtracting the second number of delay elements from the first number. Thereafter, the slave DLL is programmed with the third number of delay elements.

Claims20

Dependent claims

A method comprising:

determining a first number of delay elements in a delay locked loop (DLL) needed to provide a calibrated delay for a clock signal;
determining an integer number of half clock periods of the clock signal, if any, within the calibrated delay;
if the number of half clock periods is non-zero:
determining a second number of delay elements, the second number corresponding to the integer number of half clock periods of the clock signal;
calculating a third number of delay elements by subtracting the second number from the first number;
and
programming the DLL such that the clock signal is delayed in the DLL based on the third number of delay elements;
if the number of half clock periods is zero, programming the DLL such that the clock signal is delayed in the DLL based on the first number of delay elements.

5 more elements

An apparatus comprising:

a first register configured to store a first delay code indicating a first number of delay elements in a first delay locked loop (DLL) to provide a calibrated delay to a clock signal transmitted from a memory controller to a memory;
an arithmetic circuit configured to:
determine a number of half clock periods within the calibrated delay of the clock signal;
determine a second delay code representative of a second number of delay elements corresponding to the integer number of half clock periods of the clock signal within the calibrated delay of the clock signal;
and
calculate a third number of delay elements by subtracting the second number from the first number, wherein the third number is represented by a third delay code;
and
a second DLL configured to be programmed based on the third delay code, wherein the third number of delay elements is equal to the first number of delay elements if the integer number of half clock periods of the clock signal is determined by the arithmetic circuit to be zero.

5 more elements

A system comprising:

a memory having a plurality of storage locations;
a memory controller coupled to write data to the memory, wherein the memory controller is configured to convey a plurality of data signals and a clock signal to the memory, wherein the memory controller includes master and slave delay locked loops (DLLs) configured to control a delay of the clock signal, and wherein the memory controller further includes:
a first register configured to store a first delay code indicating a first number of delay elements in a first delay locked loop (DLL) to provide a calibrated delay to the clock signal;
an arithmetic circuit configured to:
determine a number of half clock periods within the calibrated delay of the clock signal;
determine a second delay code representative of a second number of delay elements corresponding to the integer number of half clock periods of the clock signal within the calibrated delay of the clock signal;
and
calculate a third number of delay elements by subtracting the second number from the first number, wherein the third number is represented by a third delay code;
and
a second DLL configured to be programmed based on the third delay code, wherein the third number of delay elements is equal to the first number of delay elements if the integer number of half clock periods of the clock signal is determined by the arithmetic circuit to be zero.

7 more elements

Dependencies are inferred from the claim text.

Memory controller half-clock delay adjustment

Life of this patent

Memory controller half-clock delay adjustment

Life of this patent

Abstract

Claims20