Memory system and assembling method of memory system
AssigneeKabushiki Kaisha Toshiba
InventorsYoshikazu Takeyama, Yuji Nagai
Life of this patent
Estimating the term…
Abstract
According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.
Claims14
A memory system comprising:
- a memory package including a plurality of memory chips, each of the memory chips including a non-volatile memory cell array;
- and
- a controller configured to select one memory chip from the memory package based on a chip enable and a chip address, wherein
- each of the memory chips includes
- a first storage unit configured to store therein first information that is n-bit information (n is an integer of 2 or more) compared to the chip address, the first information being used for identifying its own memory chip,
- a second storage unit configured to store therein second information for determining an effective bit of the n-bit first information, and
- a control unit configured to determine an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.
A memory package including a plurality of memory chips, each of the memory chips including a non-volatile memory cell array, wherein
- each of the memory chips includes
- a first storage unit configured to store therein first information that is n-bit information (n is an integer of 2 or more) compared to the chip address, the first information being used for identifying its own memory chip,
- a second storage unit configured to store therein second information for determining an effective bit of the n-bit first information, and
- a control unit configured to determine an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.
An assembling method of a memory system that assembles a memory package and a controller, the memory package including a plurality of memory chips, each of the memory chips including a non-volatile memory cell array, the controller selecting one memory chip from the memory package based on a chip enable and a chip address, the assembling method comprising:
- changing of second information that is stored in the non-volatile memory cell array, the second information being used for determining an effective bit of n-bit first information (n is an integer of 2 or more), the n-bit first information being a comparison target of the chip address;
- and
- connecting a chip enable pin of the controller to a chip enable pin of the memory package by wires corresponding to the changing of the second information.
Dependencies are inferred from the claim text.